Manny Sifakis Named Qualcomm Representative To Si2 OpenAccess Coalition

Emmanuel (Manny) Sifakis has been named Qualcomm’s representative to the Si2 OpenAccess Coalition.  Manny is currently senior staff engineering manager at Qualcomm, where he leads the CAD IP Quality and Design Management teams.

Manny has more than 15 years of experience in the VLSI field.  His roles have ranged from RTL to GDS delivery of custom and semi-custom designs to CAD flow and infrastructure design and development.

Si2 OpenAccess, the world’s most widely used, open-reference database for IC design, creates authentic interoperability between EDA companies and semiconductor designers and manufacturers.

Si2 Compact Model Coalition Offers Automatic Rule-Checking Software to Members and Developers

CMC Technical Advisor Geoffrey Coram of Analog Devices has developed and contributed device model rule-enforcing software to Si2. Known as Verilog-A Model Pythonic Rule Enforcer, or VAMPyRE, the software is a standalone compact model parser and checker written in Python.

VAMPyRE checks compact model implementation for a variety of problematic errors, such as hidden-state variables, bias-dependent switch branches, integer division, and unused parameters or variables. VAMPyRE also reviews the style of code, suggesting proper indentation and complaining about extra spaces or tabs. Resolving such errors during development can lead to dramatic time and cost savings during production.

“Commercial simulators generally just run Verilog-A models and are not usually concerned about unused parameters or poor coding style,” Coram said. “But sometimes an ‘unused’ parameter is an indication of an error, because that parameter should have been used in an equation.”  The tool is expected to bring benefits to multiple audiences: model developers want help during code development while EDA vendors would like a consistent coding style to help their optimization. Other CMC members want to verify compliance with the CMC’s Verilog-A Code Standards Policy, which was approved last fall.

CMC Chair Peter Lee agreed. “VAMPyRE is invaluable to enable the development of model code to meet the highest level of quality expected from the models standardized by the CMC. Due to these standard models being widely used in the semiconductor industry, issues with the code can potentially have a large impact to the semiconductor design business. VAMPyRE has already found errors in beta code under development of existing models before release, and we look forward to further improving and enhancing our current and next-generation models with VAMPyRE.”

To encourage widespread adoption, Si2 is offering VAMPyRE to CMC members and model developers under an open-source license.

Si2 Publishes White Paper on Expanding Use of AI/ML in Semiconductor Electronic Design

A new Silicon Integration Initiative white paper identifies a common data model as the most critical need to accelerate the use of artificial intelligence and machine learning in semiconductor electronic design automation.

The white paper, produced by a 20-member Si2 Special Interest Group, reports on findings of a global survey that identifies planned usage and structural gaps for AI and ML in EDA. It is available at  https://si2.org/product/collaborative-data-model/

Leigh Anne Clevenger, Si2 senior data scientist, said that the white paper identifies “a standard, common model for classifying and structuring machine learning and inference data as being crucial to accelerating the use of AI/ML in EDA. This data model would provide a foundation for addressing the data organization gap for chip developers, EDA tool developers, IP providers, and researchers. It would support design data and derived data for high-interest use cases.”

The survey also identifies a common reference flow, on-line AI/ML courses and organized training data as industry needs.

The white paper addresses:

  • Machine Learning and IC Design
  • Demand for Data
  • Structure of a Data Model
  • A Unified Data Model: Digital and Analog Examples
  • Definition and Characteristics of Derived Data for ML Applications
  • Need for IP Protection
  • Unique Requirements for Inferencing Models
  • Key Analysis Domains
  • Conclusions and Proposed Future Work

Member of the Si2 Special Interest Group include:

  • Advanced Micro Devices
  • Ansys
  • Cadence Design Systems
  • GLOBALFOUNDRIES
  • Hewlett Packard Enterprise
  • IBM
  • Intel Corp.
  • Intento Design
  • Keysight Technologies
  • Mentor, a Siemens Business
  • NC State University
  • PDF Solutions
  • Qualcomm
  • Samsung
  • Sandia National Laboratories
  • Silvaco
  • SK Hynix
  • Synopsys
  • Texas Instruments
  • Thrace Systems

 

Rahul Goyal of Intel Re-elected Board Chair of Silicon Integration Initiative

AUSTIN, Texas — Rahul Goyal, vice president and director of R&D strategic enablement at Intel, has been re-elected to a one-year term as chairman of the board of directors of Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

Besides Intel, other companies represented on the Si2 board are: Ansys, Cadence Design Systems, GLOBALFOUNDRIES, Google, IBM, Mentor-a Siemens Business, Qualcomm Technologies, Samsung, Synopsys and Texas Instruments.

John Ellis, Si2 president and CEO, said Goyal’s re-election “provides sustained leadership as we continue to advance with our members into artificial intelligence and machine learning, 5G, and autonomous vehicles, as well as assure continuity and stability during the disruption that COVID has inflicted on our industry.”

Goyal has global responsibility at Intel for strategic sourcing, supply chain strategy, strategic collaborations, ecosystem enablement, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Si2 Announces 2020 Power of Partnerships Award Winners

AUSTIN, Texas – Semiconductor design experts from industry and academia are this year’s winners of the Silicon Integration Initiative’s Power of Partnerships Award, recognizing the Si2 team that has made the most significant contributions to the field of electronic design automation.

Led by Jerry Frenkil, Si2 director of OpenStandards, members of the Unified Power Model Working Group are being honored for developing Si2 UPM, a system-level power modeling standard which helps designers describe, analyze, and control power consumption, critical factors in reducing overall design costs and increasing chip performance.

Honorees from the UPM Working Group are:

  • Nagu Dhanwada, senior technical staff member, IBM, Working Group Chair
  • Allen Baker, lead software developer, Ansys
  • Daniel Cross, principal solutions engineer, Cadence Design Systems
  • Rhett Davis, professor of Electrical and Computer Engineering, NC State University
  • David Ratchkov, founder and CEO, Thrace Systems

UPM was created under the auspices of the OpenStandards Coalition, a technology incubator developing critical enabling technologies for fast-track industry approval toward standardization. Frenkil said the working group “has pioneered new methods for power modeling and analysis, leading to increased power efficiency. This has created new opportunities for system architects, SoC designers, IP providers, and EDA developers to estimate and control power consumption, especially at the system level.”

UPM led directly to the creation of the IEEE Standard for Power Modeling to Enable System Level Analysis, or IEEE 2416-2019. This standard is based almost entirely on the efforts of the UPM working group.

Each Si2 coalition nominates one team for the annual Power of Partnerships award, which spotlights the essential role volunteers from Si2 member companies play in Si2’s continuing success and value to the industry. The Si2 board of directors selects the winners.

Runners up for 2020 are:

Compact Model Coalition, Open Model Interface Working Group
Chair, Colin Shaw, Silvaco

Contributed to Si2 initially by Taiwan Semiconductor Manufacturing Company, OMI is built around the TSMC Model Interface. OMI allows circuit designers to simulate and analyze such significant physical effects as self-heating and aging, and to perform extended design optimizations, including statistical modeling of process variations.

OpenAccess Coalition, Polygon Operators Working Group
Chair, James Masters, Intel

The Polygon Operators Working Group develops oaxPop, an API extension used with Si2 OpenAccess, the world’s most widely used open reference database for IC design. Originally contributed to Si2 by Intel, oaxPop brings the power of the popular Boost Polygon Library into the expanding OpenAccess design database ecosystem.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Executives from Siemens, Qualcomm and Samsung Join Si2 Board of Directors

AUSTIN, Texas—Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for semiconductor design tools, announced today the election of its 2020-2021 board of directors.

Joining the Si2 board this year are:

  • Juan C. Rey, vice president of Engineering, Mentor, a Siemens Business
  • Pankaj Kukkal, vice president, EDA, Emulation and Post-Silicon Engineering, Qualcomm Technologies
  • Jung Yun Choi, corporate vice president, Electronics Design Technology, Samsung Electronics

Re-elected board members are:

  • Vic Kulkarni, vice president and chief strategist, Ansys
  • Stanley Krolikoski, fellow, Ecosystems, Cadence Design Systems
  • Richard Trihy, vice president, Design Enablement, GLOBALFOUNDRIES
  • Roger Carpenter, hardware engineer, Google
  • Leon Stok, vice president, Electronic Design Automation Technologies, IBM
  • Rahul Goyal, vice president, Intel Corp., director, R&D Strategic Enablement
  • David DeMaria, corporate vice president, Strategic Initiatives and Market Intelligence, Synopsys
  • Keith Green, distinguished member of the technical staff, Texas Instruments

The Si2 board represents leading semiconductor manufacturers and foundries, fabless companies and EDA software providers.  Si2’s key programs include: OpenAccess—a standard application programming interface and reference source code for the design database used by all major chip design software suppliers; and the Compact Model Coalition, which selects and supports industry-standard SPICE simulation models.

About Si2

Founded in 1988, Si2 provides standard interoperability solutions for semiconductor design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Jeff Brubaker of Synopsys Joins Si2 OpenAccess Change Team

Jeff Brubaker, infrastructure architect for Custom Compiler at Synopsys, has been elected to the Si2 OpenAccess Change Team. OpenAccess, the world’s most widely used, open-reference database for IC design, creates authentic interoperability between EDA companies and semiconductor designers and manufacturers.

Jeff started working on custom design tools at Avanti in 2000 and joined Synopsys in 2002. In 2004, he was on the Synopsys team which started the product that eventually became Custom Compiler–the Synopsys design environment for full-custom analog, custom digital, and mixed-signal IC design. He has worked with OpenAccess since 2005 and currently manages the Synopsys team responsible for OpenAccess-related development and maintenance.

Si2 Launches Survey on Artificial Intelligence and Machine Learning in EDA

Si2 has launched an industry-wide survey to identify planned usage and structural gaps for prioritizing and implementing artificial intelligence and machine learning in semiconductor electronic design automation.

The survey is organized by a recently formed Si2 Special Interest Group chaired by Joydip Das, senior engineer, Samsung Electronics, and co-chaired by Kerim Kalafala, senior technical staff member, EDA, and master inventor, IBM. The 18-member group will identify where industry collaboration will help eliminate deficiencies caused by a lack of common languages, data models, labels, and access to robust and categorized training data.

This SIG is open to all Si2 members. Current members include:

  • Advanced Micro Devices
  • ANSYS
  • Cadence Design Systems
  • Hewlett Packard Enterprise
  • IBM
  • Intel
  • Intento Design
  • Keysight Technologies
  • Mentor, a Siemens Business
  • NC State University
  • PFD Solutions
  • Qualcomm
  • Samsung Electronics
  • Sandia National Laboratories
  • Silvaco
  • Synopsys
  • Thrace Systems
  • Texas Instruments

The survey is open April 15 – May 15.

The survey link is:  https://bit.ly/SI2_AI_ML_Survey

Leigh Anne Clevenger, Si2 senior data scientist, said that the survey results would help prioritize SIG activities and timelines. “The SIG will identify and develop requirements for standards that ensure data and software interoperability, enabling the most efficient design flows for production,” Clevenger said. “The ultimate goal is to remove duplicative work and the need for data model translators, and focus on opening avenues for breakthroughs from suppliers and users alike.”

“High manufacturing costs and the growing complexity of chip development are spurring disruptive technologies such as AI and ML,” Clevenger explained. “The Si2 platform provides a unique opportunity for semiconductor companies, EDA suppliers and IP providers to voice their needs and focus resources on common solutions, including enabling and leveraging university research.

Support for OpenAccess 22.50 Ends in June

Effective June 1, 2020, OpenAccess 22.50 (DM5) will no longer be supported and no further source code changes will be made.

What this means for OpenAccess Coalition Members

The present OA 22.50 releases will be available for the near future, although members should consider plans to migrate to the new OpenAccess 22.60 (DM6). The migration plan is well designed as your OA 22.50 database still works in 22.60.

Should you choose to use the new data model features of OA 22.60 your database will become a DM6 database and can only be read with 22.60.

Going forward, the focus will be on the new OA22.60 data model. This includes support for C++ 11. New oaPartitions classes enable performance and portability enhancements to your applications, including parallel execution with partial loading of data.

The 4G limits have been relaxed on polygon point data and certain types of application defined data. In most cases, databases written by OA 22.60 will remain DM5/OA 22.50 compatible. OA 22.60 will only write a DM6 database if:

  • more than 4G of oaAppProp or oaPointArray data is used or,
  • oaPartitions are created

For more information contact Marshall Tiner, director of Production Standards, mtiner@si2.org.

Si2 Compact Model Coalition to Support CEA-Leti SPICE Simulation Model

The Si2 Compact Model Coalition has announced the approval and financial support of L-UTSOI, a new ultra-thin, silicon-on-insulator transistor simulation model developed by CEA-Leti, a France-based research institute for electronics and information technologies.

L-UTSOI was selected for support by CMC, a coalition of 30 semiconductor companies that standardizes semiconductor models used in a class of circuit simulation tools called SPICE, or Simulation Program with Integration Circuit Emphasis. Manufacturers save time and money by simulating the performance of new or enhanced integrated circuit designs before the ICs are manufactured. The CMC funds leading universities and research institutions to develop, refine and maintain SPICE models, which are incorporated into widely used semiconductor design tools.

Silicon-on-insulator uses a thin layer of insulating oxide that semiconductor manufacturers insert between a silicon substrate and the top silicon layer. That insulating layer improves power efficiency and reliability. When compared with conventional bulk-silicon CMOS devices, SOI designs are well-suited for low-cost, low-power applications, such as automotive and the Internet of Things.

“CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.”

André Juge, working group co-chair and fellow member of technical staff at STMicroelectronics, stated, “L-UTSOI features accurate modeling of ultra-thin body and box fully-depleted SOI devices, combined with high predictiveness and numerical performance for simulation of circuits operating in a wide range of applications. For several years, starting at the 28-nanometer technology node and below, L-UTSOI has been a key enabler for design technology co-optimization.”

“CMC provides a rare opportunity to work in tandem with the simulator suppliers that are implementing our code, and the end-users which create the designs,” said Thierry Poiroux, head of the Simulation and Compact Modeling Laboratory at CEA-Leti. “Regular CMC meetings ensure a quick response to feature and bug-fix requests. We look forward to this same support from the CMC stakeholders implementing and using the L-UTSOI model.”

“As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer request for model support, as we continue to add value to their membership. ”