Si2 Compact Model Coalition to Support CEA-Leti SPICE Simulation Model

The Si2 Compact Model Coalition has announced the approval and financial support of L-UTSOI, a new ultra-thin, silicon-on-insulator transistor simulation model developed by CEA-Leti, a France-based research institute for electronics and information technologies.

L-UTSOI was selected for support by CMC, a coalition of 30 semiconductor companies that standardizes semiconductor models used in a class of circuit simulation tools called SPICE, or Simulation Program with Integration Circuit Emphasis. Manufacturers save time and money by simulating the performance of new or enhanced integrated circuit designs before the ICs are manufactured. The CMC funds leading universities and research institutions to develop, refine and maintain SPICE models, which are incorporated into widely used semiconductor design tools.

Silicon-on-insulator uses a thin layer of insulating oxide that semiconductor manufacturers insert between a silicon substrate and the top silicon layer. That insulating layer improves power efficiency and reliability. When compared with conventional bulk-silicon CMOS devices, SOI designs are well-suited for low-cost, low-power applications, such as automotive and the Internet of Things.

“CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.”

André Juge, working group co-chair and fellow member of technical staff at STMicroelectronics, stated, “L-UTSOI features accurate modeling of ultra-thin body and box fully-depleted SOI devices, combined with high predictiveness and numerical performance for simulation of circuits operating in a wide range of applications. For several years, starting at the 28-nanometer technology node and below, L-UTSOI has been a key enabler for design technology co-optimization.”

“CMC provides a rare opportunity to work in tandem with the simulator suppliers that are implementing our code, and the end-users which create the designs,” said Thierry Poiroux, head of the Simulation and Compact Modeling Laboratory at CEA-Leti. “Regular CMC meetings ensure a quick response to feature and bug-fix requests. We look forward to this same support from the CMC stakeholders implementing and using the L-UTSOI model.”

“As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer request for model support, as we continue to add value to their membership. ”

Samsung Executive Joins Si2 Board of Directors

Jung Yun Choi, corporate vice president for the Samsung Electronics Design Technology team, has been elected to the Silicon Integration Initiative board of directors.

A 17-year Samsung veteran, Choi leads the team responsible for developing all design tools and methodologies for Samsung memory products: technologies and environments impacting product values, new process and package technologies, new applications and new working environments such as the Cloud.

Since joining Samsung, he has contributed to the development of low-power design methodologies for mobile devices, RTL-to-GDS implementation and sign-off methodologies.

Choi joined Samsung Electronics in 2003 after receiving his doctorate in electrical engineering at the Pohang University of Science and Technology, Republic of Korea. He was a visiting scholar at Stanford University in 2012.

John Ellis, Si2 president and CEO, said, “Doctor Choi brings a unique, IDM and foundry perspective to Si2. His in-depth understanding of fundamental semiconductor principles, along with his hands-on experience in product development, including our current thrust in system-level power modeling for low-power design, will be extremely valuable as we develop our direction for the future.”

SI2 Launches Special Interest Group For AI and ML in Electronic Design Automation

SIG Will Fill Industry Gaps to Enable Artificial Intelligence and Machine Learning in EDA

Silicon Integration Initiative has launched a special interest group to focus on the growing needs and opportunities in artificial intelligence and machine learning for electronic design automation.

The group will identify current solutions and technology gaps in AI and ML strategies for EDA digital design. “AI and ML are changing semiconductor design and improving performance and time to market,” said Leigh Anne Clevenger, Si2 design automation data scientist.  “Based on member company interest, we expect the SIG to propose prototype projects to accelerate the development of standards in areas such as machine learning training, and data handling and sharing.

“High manufacturing costs and the growing complexity of chip development are spurring disruptive technologies such as AI and ML,” Clevenger explained. “Si2 provides a unique opportunity for semiconductor companies, EDA suppliers and IP providers to voice their needs and focus resources on common solutions, including leveraging university research.”

The SIG is open to all Si2 members and is chaired by Joydip Das, Senior Engineer I, Samsung Austin R&D Center, and co-chaired by Kerim Kalafala, senior technical staff member, EDA, IBM.

“In recent years, the EDA industry has significantly expanded the use of AI/ML technology and techniques in its design tools,” said Das. “We’ve identified the need for a common industry-wide infrastructure to help share this information. This will help eliminate duplicative work and open up avenues for new breakthroughs.”

Other Si2 members participating in the SIG include: Advanced Micro Devices, ANSYS, Cadence Design Systems, Hewlett Packard Enterprise, Intel, Intento Design, NC State University, PDF Solutions, Sandia Labs, Synopsys and the University of California, Berkeley.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. Its activities include support of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

New Version of Si2 oaScript Expands IC Design Capabilities into the Cloud and AI

Design partitioning and multi-threaded parallel execution are key features of the updated scripting interface to OpenAccess, the industry’s most widely used IC design database. oaScript Version 4.0—developed by programming experts in the Silicon Integration Initiative oaScript Working Group—leverages the powerful enhancements available to OpenAccess in its most recent Data Model 6 upgrade.

“Our oaScript Working Group spent considerable time working through implementation details for optimal use in each supported scripting language”

“oaPartitions allows an application to rapidly load design instances, shapes, or vias from a given partition without loading an entire design. An application can define partitions by any criteria the developer prefers—by geography, by layer, or even alphabetically. In addition to creating partitions, applications now have access to all of the OpenAccess classes needed to work with partitions, including the partition array class,” Tiner explained.

Flexible partitions can enhance multi-threading capabilities, helping avoid collisions between design-segregated threads. For example, an application could explicitly assign a dedicated thread to each design layer, virtually guaranteeing no thread collisions. “This is very significant for applications utilizing parallel execution techniques,” Tiner added.

“Our oaScript Working Group spent considerable time working through implementation details for optimal use in each supported scripting language,” Tiner said. “As this group is made up of top EDA developers in the industry, each from unique and sometimes competing companies, their ability to collaborate is a stellar example of the value our members bring to Si2, and the strengths Si2 brings to its members.”

Rudy Albachten of Intel, chair of the oaScript Working Group, said, “With improved support for the latest versions of Python and Ruby, along with continued support for perl and tcl, oaScript 4.0 gives developers easy access to the full capabilities of the OpenAccess database. I am very proud of the hard work from the multi-company collaborative working group, and excited to see interest in using oaScript for diverse applications—including AI with Tensor Flow, using oaScript in the Anaconda platform, and usage in virtual machine environments. OaScript continues to enable designers and developers to quickly prototype custom tools. Enabling the new partitioning and multi-tasking capabilities of OpenAccess is an exciting new capability.”

Qualcomm Executive Joins Si2 Board of Directors

Pankaj Kukkal, vice president of Engineering at Qualcomm Inc., has been elected to the Silicon Integration Initiative board of directors. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

In his current role, Kukkal oversees all EDA, emulation and post-silicon engineering functions for mobile, compute, automotive, and artificial intelligence/machine learning business units. He joined Qualcomm in 2012. He has contributed to delivering over 50 leading-edge SoCs in various application domains.

Kukkal has more than 25 years of experience in EDA, silicon, systems, and software engineering. Before joining Qualcomm, he held various leadership positions at Intel, focusing on CAD, emulation and validation. He has led the creation of several industry-leading technologies for chip design, emulation and post-silicon debug and automation.

Kukkal has a bachelor’s degree in electrical engineering from the National Institutes of Technology, India, and a master’s degree in computer engineering from the University of South Carolina.

John Ellis, president and CEO, said Kukkal brings crucial experience and domain knowledge to the Si2 board.  “Pankaj has been in key, strategic roles at Qualcomm and Intel over his long career. The insights he has gained, along with his extensive network of contacts including former associates, customers and suppliers in the semiconductor industry, will be invaluable as Si2 and its board maps out where the industry is going, and what Si2 members need from us to help propel them there most efficiently.”

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.


Si2 Compact Model Coalition Releases BSIM-CMG SPICE Model for Advanced IC Designs

CMC Members Benefit from 18-Month Early Access to New Standard Model

AUSTIN, Texas — The Si2 Compact Model Coalition has released the latest version of BSIM-CMG FinFET, a standard compact SPICE model developed by researchers at the University of California, Berkeley, in conjunction with 20 partners from many of the industry’s leading semiconductor companies.

CMC is a collaborative industry group that standardizes SPICE (Simulation Program with Integration Circuit Emphasis) device models.

John Ellis, Si2 president and CEO, said FinFET is the transistor design that powers the industry along Moore’s Law to advanced leading-edge integrated circuits, including the latest 7nm chips used in every new smartphone, tablet, server, and personal computer. “The industry-standard SPICE model for FinFET is the 3D multi-gate transistor, a critical part of the ecosystem. Its sophistication required a cross-industry team to bring this model to fruition,” Ellis said.

“FinFET” refers to a visual description of a multi-gate, non-planar transistor. In IC design, field-effect-transistor gates wrap around the three sides of a vertical, fin-like channel, creating conducting channels on all sides of the structure. FinFET was named by Dr. Chenming Hu, a National Medal of Technology and Innovation recipient and professor emeritus in the Electronic Engineering and Computer Science Department at UC Berkeley.

“The model updates in the new release (111.0.0) are important refinements and fixes,” stated CMC BSIM-CMG working group chair, Richard Williams. “This new release will benefit all BSIM-CMG users in its myriad applications.” Through the CMC—­and working under Si2’s anti-trust umbrella as a collaborative R&D joint venture—university researchers, simulation software suppliers, fabless, foundry and integrated device manufacturers team up to produce a variety of industry-standard models. CMC members have immediate access to new standards, while new standards are released to the public 18 months after initial release.

Dr. Harshit Agarwal, a post-doctoral developer at UC Berkeley states, “CMC provides a tie to the industry that keeps us in close touch with the customer’s needs. Without CMC there’s no shared funding to support our model standardization, and the data, testing, and feedback on model performance would have to be sought after on a company-by-company basis. Together we are all much more intelligent and customers can cooperatively prioritize their requested features and bug fixes. Beyond this, the quality assurance program provided by CMC ensures our model, and the simulator provider’s implementations, perform at their absolute best for the designers.”

Dr. Peter Lee, CMC chair, agreed and added, “It has been two-and-a-half years since the last major BSIM-CMG update, which is equivalent to a semiconductor generation or two. This new version implements 25 enhancements and 13 bug fixes which improve accuracy, convergence, and performance when compared to the previous version. These changes can have important implications in shortening design time and ensuring first silicon success for a wide variety of products.”

Enhancements include improvements to the thermal noise model and the introduction of gate current scaling factors. Bug fixes include corrected parameter range, and use of macros instead “ifdef’s”, making the code even more robust.


About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Microsoft, GLOBALFOUNDRIES Join Si2 OpenAccess Coalition

Growing Membership Shows Ongoing Vertical Integration in IC Design

Austin, Texas—Microsoft Corporation and GLOBALFOUNDRIES have joined Silicon Integration Initiative’s OpenAccess Coalition, a diverse group of international semiconductor companies that support the OpenAccess design database application programming interface.

OpenAccess, which was introduced in 2002, is the most widely used IC design database and is currently supported by its 43 members, representing semiconductors manufacturers and foundries, fabless companies, EDA software providers and systems houses. The OpenAccess database provides EDA software tools with immediate design flow interoperability, saving members time and money.

John Ellis, Si2 president and CEO, said that the recent addition of Microsoft—and Google last year—illustrates the continuing trend of IC design vertical integration. He cited a recent Si2 industry survey which showed “that more than 80 percent of end users develop specialized, internal design tools. OpenAccess allows these home-grown tools to fit into the company’s own, optimized design flow, integrating the best-in-class EDA tools without sacrificing interoperability or performance.

“These end-users are often most interested in the OpenAccess scripting-language interface, which gives engineers direct access into their OA-based design through, for example, the Python programming language,” Ellis said. “This makes their design directly accessible from the console, or rapidly prototyped scripts. Python is well-known and widely adopted by programmers, and has many libraries and tools available, including popular AI development toolkits. The new code release supports these and provides a path toward developing machine-learning-based EDA tools which can make use of the OA database for training.”

Si2 recently introduced OpenAccess Data Model 6, the first major code revision since 2014. DM6 features oaPartitions, a new addition which allows multiprocessing capability to be applied simultaneously to smaller, partitioned regions in large chip designs. Early-stage performance benchmarking by Dr. Rhett Davis from N.C. State University, which was presented at the recent Design Automation Conference, showed under certain circumstances a more than 10x processing speed improvement over the prior version of OpenAccess. DM6 provides a path to higher-efficiency design. Its multiprocessing capability enables cloud-centric design flows for EDA tools which are based on the OpenAccess database.

IEEE Approves New Power Modeling Standard. 2416-2019 Built on Si2 Unified Power Model

AUSTIN, Texas–Silicon Integration Initiative has announced that its Unified Power Model, developed with major contributions from IBM and GLOBALFOUNDRIES, has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018 Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems.

Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

UPM/IEEE 2416-2019 provides a rich set of power modeling semantics enabling system designers to model entire systems with great flexibility. It supports power modeling from abstract design description all the way to gate level implementation providing data consistency from earliest architectural explorations to final power verification.

“We view UPM/IEEE 2416 as a major step forward for low power design,” commented Dr. Nagu Dhanwada of IBM, chair of the IEEE 2416 and the Si2 UPM Working Groups.

“The foundation of the UPM/IEEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors. Concepts like multi-level, state-based modeling and efficient, expressive semantics in UPM/IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” stated Dr. Dhanwada.

Si2 UPM is a product of the Si2 OpenStandards Coalition, an R&D incubator which rapidly seeds and prototypes potential new EDA software tool interoperability standards. “The target of this development and subsequent standardization was an efficient and flexible mechanism for the specification and interchange of consistent power models throughout a project’s lifetime, from system design to manufacturing, especially for IP blocks and chiplets,” said Jerry Frenkil, Si2 director of OpenStandards. “This work led to significant advances in power modeling, including contributor and multi-level modeling, both of which are included in the 2416-2019 standard.”

A prototype power tool, upmPowerCalc, was built to prove the new concepts from end-to-end, both accelerating the delivery of a ready-to-implement standard and providing OpenStandards members with tools to aid in their own implementation.” The Si2 work was supported by the UPM Working Group consisting of ANSYS, IBM, Intel, Cadence, Entasys, and Thrace Systems.

Power contributors are Process, Voltage, and Temperature independent proxies for power. This PVT independence enables the late binding of PVT conditions at simulation run time, enabling power analysis at various PVT corners without requiring new libraries. Multi-level models provide multiple model views, or interfaces, to access the same power data. With multi-level construction, a single model provides consistent data for both system-level abstract simulations and bit-level simulations with RTL or gates.

“These advancements, along with UPM’s semantic expressiveness, deliver multiple benefits for design organizations” Frenkil explained. “System architects and SoC designers can model entire systems at a variety of PVT points with great flexibility. Power can be modeled in UPM using scalars, tables, expressions, and contributors, as well as expressions referencing contributors.”

UPM’s expressiveness also provides major benefits for IP developers. The use of power contributors leads to significant productivity gains since far fewer models and libraries are needed with UPM’s PVT independence. In addition, the models are abstract black boxes – functionality cannot be reverse-engineered from the power models.

Model interoperability and consistency with UPF/IEEE 1801 were identified early on as key goals in support of increasing emphasis on system level design. “IEEE 2416 provides a standardized interoperable system-level power model that is an essential piece of the foundation of an emerging industry-scale chiplet ecosystem” commented Ramune Nagisetty, senior principal engineer and director of Process and Product Integration at Intel Corporation.

“Energy-aware, system-level design can be a challenging task,” added John Biggs, chair of the IEEE P1801 Working Group, and distinguished engineer and co-founder of Arm. “With this new standard, designers will be better enabled by having access to semiconductor IP delivered with both IEEE 1801 power state models and IEEE 2416 power data models.”

For design automation groups, UPM provides an industry-standard format for both internal and external IP. This common format saves resources and time as there is no need to support or translate external proprietary formats. UPM also reduces reliance on internal proprietary formats, a long-standing design obsolescence trap.

An EDA startup, Thrace Systems, is planning to add IEEE 2416 support to its products. “UPM/IEEE 2416 is an important new standard. Its rich modeling semantics provide our power analysis platform with the solid infrastructure needed for comprehensive system level analysis,” commented David Ratchkov, Thrace Systems founder and CEO.

The P2416 Working Group was led by IBM, Si2, and Cadence, with active support from Intel and Arm.

For more information contact Jerry Frenkil at

Rahul Goyal of Intel Re-elected Board Chair of Silicon Integration Initiative

AUSTIN, Texas — Rahul Goyal of Intel has been reelected to a one-year term as board chair of Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

Other companies represented on the Si2 board are: ANSYS, Cadence Design Systems, GLOBALFOUNDRIES, Google, IBM, Qualcomm Technologies, Samsung, Siemens–a Mentor Business, Synopsys and Texas Instruments.

John Ellis, Si2 president and CEO, said Goyal’s reelection “will assure leadership continuity as we expand support for our members into such advanced technologies as artificial intelligence, machine learning, and design in the cloud.”

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, Electronic Design Automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

Si2 Elects Board Members for 2019-2020

Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools, announced today the election of the 2019-2020 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference, June 3, 4:00 – 5:30 p.m., Las Vegas Westgate Hotel, Ballroom F.

Joining the Si2 Board this year is:

  • ANSYS—Vic Kulkarni, vice president and Chief Strategist, ANSYS Inc.

Re-elected board members are:

  • Cadence Design Systems—Stanley Krolikoski, fellow, Strategic Alliances
  • GLOBALFOUNDRIES—Richard Trihy, vice president, Design Enablement
  • Google—Roger Carpenter, Hardware Engineer
  • IBM—Leon Stok, vice president, Electronic Design Automation Technologies
  • Intel—Rahul Goyal, vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling
  • Mentor, a Siemens Business—Mick Tegethoff, director of Product Marketing for Analog/Mixed-Signal/RF IC Verification Solutions
  • Qualcomm Technologies—Udi Landen, vice president of Engineering
  • Samsung Electronics—Seungbum Ko, vice president, Electronics Design Technology Team
  • Synopsys—David DeMaria, vice president, Corporate Marketing
  • Texas Instruments—Keith Green, distinguished member of the technical staff, Analog Technology Development

Details on the Si2 Member Meeting and Reception and other Si2 DAC activities are available at