Views from the Cloud: Si2 Annual Technology Forum

The growing impact and productivity gains of designing semiconductors in the cloud comprise the focus the Si2 Annual Technology Forum, an online event scheduled for Friday, August 6, from 8:00 a.m. – to 10:00 a.m. Pacific Standard Time.

Registration is free. For details click here.

Silicon Integration Initiative is an R&D joint venture providing standard interoperability solutions for semiconductor design tools. Si2’s key programs include OpenAccess, a standard application programming interface and reference source code for the design database used by all major chip design software suppliers, and the Compact Model Coalition, which selects and supports industry-standard SPICE simulation models.

AGENDA

Keynote PresentationSilicon-to-System – Addressing Design, Verification, and Implementation Challenges with Cloud-Based Engineering

David Pellerin
Head of Worldwide Business Development
Hitech/Semiconductor
Amazon Web Services


Executive Panel Discussion:
EDA-in-the-Cloud Challenges are Already Solved by Providers

Kerim Kalafala
Senior Technical Staff Member
IBM

Ramond Rodriguez
Senior Director of Strategic CAD Capabilities
Intel

Dr. Rhett Davis
Professor of Computer and Electrical Engineering
NC State University

Rajeev Jain
Senior Director of Technology
Qualcomm


Si2 Technical Coalition Updates

OpenAccess, oaScript Extensions
Marshall Tiner
Si2 Director of Production Standards

Standard Compact Models
John Ellis
Si2 President and CEO

AI/ML, Unified Power Models
Dr. Leigh Anne Clevenger
Si2 Director of OpenStandards

Special Announcement

Learn about a new Si2 industry initiative focusing on silicon-to-system design interoperability

Vic Kulkarni
Si2 Chief Strategy Officer


Annual Power of Partnerships Award

Presented to the Si2 team that has made the most significant contributions to the field of electronic design automation

 

Executives from Cadence, SK Hynix Join Si2 Board of Directors

AUSTIN, Texas—Silicon Integration Initiative, a leading research and development joint venture providing standard interoperability solutions for semiconductor design tools, announced today the election of its board of directors for 2021-2022.

Joining the Si2 board for their first full terms are:

  • Aparna Dey, Senior Product Marketing Group Director, Cadence Design Systems
  • Do Chang-Ho, Vice President, Computer Aided Engineering Division, SK Hynix

Re-elected board members are:

  • Richard Trihy, vice president, Design Enablement, GLOBALFOUNDRIES
  • Roger Carpenter, hardware engineer, Google
  • Leon Stok, vice president, Electronic Design Automation Technologies, IBM
  • Rahul Goyal, vice president, Intel Corp., director, R&D Strategic Enablement
  • Pankaj Kukkal, vice president, EDA, Emulation and Post-Silicon Engineering, Qualcomm Technologies
  • Jung Yun Choi, corporate vice president, Electronics Design Technology, Samsung Electronics
  • Juan C. Rey, vice president of engineering, Calibre, Siemens EDA
  • David DeMaria, corporate vice president, Strategic Initiatives and Market Intelligence, Synopsys
  • Keith Green, distinguished member of the technical staff, Texas Instruments

The board elected prior board member, John Lee, general manager and vice-president, Ansys, as an ex-officio board member. Lee will advise the board with regards to Si2’s long-term strategy for design-in-the-cloud, as well as for artificial intelligence and machine learning-enabled design.

The Si2 board represents leading semiconductor manufacturers and foundries, fabless companies, and EDA software providers. Si2’s key programs include OpenAccess, a standard application programming interface and reference source code for the design database used by all major chip design software suppliers, and the Compact Model Coalition, which selects and supports industry-standard SPICE simulation models.

About Si2

Founded in 1988, Si2 provides standard interoperability solutions for semiconductor design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Si2 Releases New Version of oaScript Extension

Si2 has released oaScript v4.1, which contains a number of improvements to the script versions of the OpenAccess API:

  •  New oaByteArray versions of oaParam::getAppVal/oaParam::setAppVal
  • ·Support for Python-3.8, Python-3.9 and Ruby-2.7
  • New HTML language-specific documentation
For more information contact Marshall Tiner, director of Production Standards, [email protected].

Peter Lee of Micron Tapped for Si2 Pinnacle Award

Peter Lee, director of a global team responsible for the DRAM design environment at Micron Technology, will receive the quarterly Silicon Integration Initiative Pinnacle Award. This award recognizes volunteers for their exceptional contributions to Si2’s success as a leading semiconductor R&D joint venture.

Lee serves as chair of the Si2 Compact Model Coalition, an international group that supports the development of standard compact SPICE models and standard interfaces to promote simulation tool interoperability. He has led the CMC since 2016, during which time the group has partnered with leading universities and research labs to fund four new device models and 11 existing standard models adopted by semiconductor manufacturers, designers and simulation tool providers. The CMC has consistently increased overall funding to model developers under Lee’s chairmanship.

Lee has more than 30 years of device modeling and circuit-level reliability simulation experience at Micron, Elpida Memory, Renesas Technology, and Hitachi. He earned his Ph.D. in Electrical Engineering from the University of California at Berkeley and is a senior member of the IEEE.

John Ellis, Si2 president and CEO, stated, “Peter has been a leader within the CMC since they first joined forces with Si2 in 2013, first as co-chair and then as chair. It’s a pleasure to work with Peter and recognize him publicly for his diligent effort in guiding this prestigious group. Si2 is grateful to Micron for enabling Peter to continue his efforts within the CMC.”

About the Compact Model Coalition

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers an avenue to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability. CMC funds and supports select university and national laboratory compact model developers. The CMC quality assurance program ensures that simulations are accurate and uniform across different vendors. The world’s most advanced semiconductor designs are designed and simulated using the standards funded by the CMC.

About the Silicon Integration Initiative

Si2 is a leading research and development joint venture that provides standard interoperability solutions for IC design tools. Its primary products include OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Silicon Integration Initiative Targets New Silicon Carbide Standard SPICE Model

The Si2 Compact Model Coalition has voted to fund and standardize a SPICE model for silicon carbide-based metal-on-silicon field-effect transistors. Featuring high efficiency and fast operation with low switching losses, silicon carbide-based metal-on-silicon-field effect transistors are popular in high-growth semiconductor applications such as photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution.

 

Peter Lee

A CMC working group will oversee the model development as part of advancing Si2’s mission to reduce interoperability costs, said Peter Lee, CMC chair. Participating companies include Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys. The decision to launch the working group came after the CMC evaluated the model’s ROI for members and interest by the industry at large. “I’d encourage companies with a stake in SiC devices to join this effort and help guide selection of the model which best represents their intended use,” advised Lee. “They can benefit from both cost reduction that comes from shared model support and a standardized and qualified model that has ongoing bug fixes and requested feature enhancements from many like-minded companies.”

 

Colin Shaw

“Next Generation SiC MOSFETS has many features that make them suitable, and even superior to legacy silicon solutions, for several high voltage applications. While the devices can handle high-temperature and voltage, its minimal ON-resistance allows smaller packages and better energy savings than comparable silicon devices,” stated Colin Shaw from Silvaco, the working group chair.

 

 

 

 

About the Compact Model Coalition

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability. CMC funds and supports select university and national laboratory compact model developers. The CMC quality assurance program ensures that simulations are accurate and uniform across different vendors. The world’s most advanced semiconductor designs are all designed and simulated using the standards funded by the CMC.

 

About the Silicon Integration Initiative (Si2)

Si2 is a leading research and development joint venture that provides standard interoperability solutions for IC design tools. Its primary products include OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Si2 Names Vic Kulkarni Chief Strategy Officer

Vic Kulkarni, former vice president of strategy at Ansys, has joined Silicon Integration Initiative as chief strategy officer. He now supports the Si2 leadership team’s expanding opportunities as one of the semiconductor industry’s leading R&D joint ventures.

Before retiring from Ansys last month, Kulkarni was responsible for steering the business, technology, go-to-market and product strategy of the Semiconductor Business Unit. His areas of responsibility included chip-package-board and system design software solutions, multi-domain simulation technology, and AI/ML to address challenges faced by multiple verticals ranging from connectivity, 5G, autonomous, aero-defense, HPC and edge-node compute. He also drove strategic acquisitions for the Ansys leadership team.

Prior to Ansys, Kulkarni served as co-founder, president and CEO of Sequence Design, which focused on EDA solutions for power and energy-efficient chip designs. He also held a variety of engineering and senior management positions in leading semiconductor and EDA companies in Silicon Valley.

Kulkarni earned an MSEE in Solid State Electronics from the University of Cincinnati, which honored him with the “Distinguished Alumnus Award” in 2007. He has a B.Tech in Electrical Engineering from the Indian Institute of Technology, Bombay.

John Ellis, Si2 president and CEO, said Kulkarni’s time as a former Si2 board member provides an excellent backdrop for his current role. “While on the board,” Ellis said, “Vic was involved in developing a new methodology for setting Si2’s long-term strategy. In this newly created role, he will be diving even deeper into hands-on reshaping of the organization for its future sustainability and growth.”

“The duality of Moore’s Law and the More-than-Moore trend in scaling below 10 nanometers is creating a renaissance in the semiconductor industry,” Kulkarni observed. “I am honored to join John and the Si2 ecosystem in addressing crucial interoperability challenges facing the next generation of semiconductor-to-electronic system designs.”

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

Johannes Grad of Cadence First Si2 Pinnacle Award Winner

Johannes Grad, product engineer at Cadence Design Systems, is the winner of the first quarterly Pinnacle Award, presented to volunteers for exceptional contributions to Si2’s success as an R&D joint venture.

A member of the Cadence Custom IC and PCS Group, Johannes focuses on OpenAccess development, supporting advanced process nodes, and software infrastructure for physical design. He is a moderator for the Si2 OpenAccess Issue Tracking System and Discussion Forum and a member of the Si2 OA Debug Working Group. Johannes has Ph.D. in Electrical Engineering from the Illinois Institute of Technology.

Marshall Tiner, director of Production Standards, said that “Johannes’ behind-the-scenes efforts are uniquely representative of the great work done by volunteers to assure OpenAccess remains the industry’s leading design databaseAs an essential member of the Discussion Forum, whether he’s responding to a user error or lack of product knowledge, Johannes handles every problem with professionalism and tact.  He has shown unwavering support for all members of the OpenAccess Coalition.” 

Ali Sadigh Joins Si2 Technical Team; Robert Hill Named Client Account Manager

Ali Sadigh

Ali Sadigh, a technical professional with more than 25 years of experience in computational electromagnetics, circuit simulation and industrial data acquisition and management, has joined Silicon Integration Initiative as a principal software design engineer. Si2 also announced that Robert Hill has been named client account manager

Before joining Si2, Sadigh worked with AVEVA Group as part of the Historian high-performance process database. His efforts focused on cloud-based data subscription and other applications based on service-oriented architecture for time-series data storage, retrieval and analytics.

Sadigh began his career at Compact Software, working on the Microwave Explorer simulator. He then joined the IBM EDA group where his contributions were focused on API-driven simulations for timing, noise and power methodologies used in IBM semiconductor design. He then held a position at Cadence Design Systems, performing research and development on the Spectre AMS Designer. Sadigh received a doctorate in electrical engineering from Syracuse University in 1994.

 

Robert Hill

Hill is a senior technology sales professional with over 20 years of solution-selling experience and is the recipient of numerous industry awards and commendations. He has worked as an account executive for Dell, Hewlett Packard Enterprise and IBM, helping customers modernize and transform IT operations. More recently, his focus centered on multi-cloud environments.

John Ellis, Si2 president and CEO, said, “Dr. Sadigh brings valuable industry experience in design and EDA to the table, and adds critical cloud-based application experience which will help Si2 address interoperability issues for silicon-on-cloud design. The addition of Robert, with his background in both technical sales and account management, provides our members with a central point of contact for updates and opportunities about Si2 programs and services.”

 

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

 

Aparna Dey of Cadence Joins Si2 Board of Directors

Aparna Dey, senior product marketing group director at Cadence Design Systems, has been elected to the Silicon Integration Initiative board of directors. She replaces Stan Krolikoski who served on Si2’s board since 2016.

Dey is responsible for the Cadence electronic design automation and intellectual property standards activities. She also manages the participation, contribution, partnerships and relationships between Cadence and industry standards organizations, associations, and consortiums. She has been at Cadence for over 16 years in various roles in research and development, services and technical marketing.

John Ellis, Si2 president and CEO, said Dey has an “impressive record of achievement in her more than 25 years in the industry that makes her an ideal addition to the Si2 board. Aparna has volunteered on various Si2 committees since 2003 and has earned the respect of our staff and her colleagues. Most notably, she has been involved with and supported our flagship coalition, OpenAccess, since its inception.”

“Si2 has been committed to driving standards interoperability that moves the IC design industry forward, and I’m passionate about working with them to continue this effort, Dey said. “Over the years, I’ve collaborated with Si2 on standards development and participated in various coalitions. I look forward to serving on the Si2 board of directors to foster EDA interoperability and support IC design industry ecosystem growth through standards solutions.”

Before her current role, Dey was responsible for driving ASIC alliance partnerships and critical technology deployments with Cadence’s leading customers. As a senior architect in the Cadence Worldwide Methodology Services Group, she worked on multiple methodology projects on-site in Japan, Taiwan and Germany.

She also worked as an advanced R&D director at Synchronicity and was responsible for their technology strategy, product roadmap and requirements for their next-generation design database and IP management products. She was awarded a US and European patent on their Silicon IP Reuse system.

Dey holds a bachelor’s degree in electronics and telecommunication engineering from Netaji Subhas Institute of Technology, University of Delhi, India.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

Si2 Workshop Explores Global Effort to Measure AI Compute Capacity and Infrastructure

An international effort to assess artificial intelligence compute capacity and help governments make informed AI infrastructure investments is the focus of an online workshop hosted by Silicon Integration Initiative, January 29, 8:00-10:00 am PST.

Keith Strier, vice president, Worldwide AI Initiatives at NVIDIA, will discuss the AI Compute Task Force created in early 2020 by the Organisation for Economic Co-operation and Development. The OECD is a Paris-based intergovernmental economic group with 37 member countries, founded in 1961 to stimulate economic progress and world trade. The task force is developing a framework to measure and benchmark domestic AI compute capacity and other AI readiness components, including budgets and investment priorities.

Their work could also address concerns that wealthier countries are making outsized investments in AI compute capacity, possibly leading to a global compute divide that will sustain resource inequalities in a global digital economy. Strier chairs the OECD task force and has primary responsibility for the NVIDIA global public sector portfolio and the AI Nations Partnership Initiative. He also advises national and city government leaders on AI policies and infrastructure.

The workshop also features Yiorgros Makris from the University of Texas at Dallas. He will discuss how machine learning can reduce semiconductor testing costs, increase test quality, improve yield and test floor logistics, and guide designers and process engineers.

Makris is a professor of Electrical and Computer Engineering and co-founder of the NSF Industry-University Cooperative Research Center on Hardware and Embedded System Security. His research focuses on applying machine learning and statistical analysis to develop trusted and reliable integrated circuits and systems, emphasizing the analog/RF domain.

The workshop will conclude with an update on the Si2 AI/ML in EDA Special Interest Group. Speakers are Joydip Das, SIG chair and senior engineer, Samsung Austin R&D Center; and Kerim Kalafala, SIG co-chair and senior technical staff member, IBM EDA.

The workshop is open to the public and registration is free. For more information visit http://bit.ly/si2_ai_workshop.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.