Intel, Microsoft, IBM Technologists Elected to Si2 OpenAccess Coalition Leadership Posts

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Raymond Rodriguez, director of Strategic CAD Capabilities at Intel, has been elected to a one-year term as
chair of the Silicon Integration Initiative OpenAccess Coalition board of directors. Ben Bowers, principal
design engineer at Microsoft, was elected OAC vice-chair. Gregory Schaeffer, senior software engineer at IBM,
was reelected as the OpenAccess Change Team co-architect.

The board manages operational decisions for OpenAccess, the world’s most widely used open reference
database for IC design. The Change Team manages OpenAccess API modifications and database implementation.

Marshall Tiner, Si2 director of Production Standards, said “Continuing engagement of industry leaders Intel,
Microsoft and IBM bodes well for the coalition’s ongoing role in advancing semiconductor design.
Ray, Ben, and Gregory each bring years of experience and expertise to the OpenAccess board and Change Team.”

Raymond Rodriguez

A 20-year Intel veteran, Rodriguez directs a team that oversees electronic design automation,
intellectual property, test and measurement, and security assurance supplier engagements.
He has been an OAC board member since 2012. His volunteer industry experience includes
general chair of the IEEE Electronic Design Process Symposium (2019-2021) and executive
committee member of the Design Automation Conference (2015-2017). Rodriguez has a BSEE
from the University of California, Los Angeles, and an MBA, Executive Program, from the
W.P. Carey School of Business, Arizona State University.

 

Ben Bowers

Bowers joined Microsoft in 2018 after 11 years at Qualcomm. He is a technical lead on a
Microsoft custom circuit CAD team that focuses on all aspects of the design flow, including
PDKs, circuit design, and simulation to physical design. He earned a BSEE from Louisiana
State University and an MSEE from Mississippi State University. He also holds 25 patents
in circuit design and methodology.

 

 

Gregory Schaeffer

In his time at IBM, Schaeffer has held various development and leadership roles in
timing/noise/electrical analysis and physical design tools and holds 21 patents in
these areas. He is the architect of IBM’s Microprocessor back-end construction methodology
and has been involved with Si2 initiatives since 2009. Schaeffer earned a BS and
MS in Computer Science from Case Western Reserve University in 2002.

 

 

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard
interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under
the auspices of The National Cooperative Research and Production Act of 1993, the fundamental
law that defines R&D joint ventures and offers them a large measure of protection against federal
antitrust laws. The Si2 international membership includes semiconductor foundries, fabless
manufacturers, and EDA companies.

Dr. Leigh Anne Clevenger Named Si2 Director, OpenStandards

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Silicon Integration Initiative has selected Dr. Leigh Anne Clevenger as director of OpenStandards, effective January 1, 2021. She will replace Jerry Frenkil, who has served in this role since 2015. Frenkil will remain with Si2 as an advisor to staff, board, and member companies on adoption of the IEEE 2416 Unified Power Modeling Standard.

Since joining Si2 in 2018, Clevenger has been the lead developer of the Si2 prototype power calculator, demonstrating the UPM/IEEE-2416 standard. She will continue to drive the UPM working group toward its goals of developing and adopting the standard. Additionally, leveraging her doctorate in Software She will continue to drive the UPM working group toward its goals of enhancement and adoption of the standard. and Machine Learning, Clevenger is currently spearheading the effort to identify and solve industry needs in applying artificial intelligence and machine learning to electronic design automation tools.

With this promotion, Clevenger will continue working directly with Si2 members and industry leaders to identify and solve issues in semiconductor design flow interoperability. As an R&D Joint Venture providing antitrust protection for its members, Si2 is uniquely positioned to organize collaborative efforts, with the ultimate goal of widespread adoption of standards providing EDA tool interoperability and customer data access.

“Starting the Special Interest Group on AI/ML in EDA served as Leigh Anne’s introduction to the role Si2 has as an R&D Joint Venture,” said John Ellis, president and CEO. “Through a series of interviews with Si2 member companies, she established a vision of the technical collaboration needed and the highest priority issues for the SIG to tackle.

“Leigh Anne has been a vital addition to our team. She added value to our operations from day one, applying her semiconductor experience to UPM coding. Following Si2’s growth path, we soon put her advanced AI/ML degree to use,” Ellis added. “The SIG she formed with industry experts is well on its way to closing some serious gaps found for effectively applying AI/ML to EDA. I look forward to what’s next for Leigh Anne. With her skills and drive, I expect great things.”

Clevenger, who earned her doctorate at Pace University, has published and presented research on data science including big data analytics, machine learning algorithms, and wearable computing. She brings to Si2 extensive experience in semiconductor design automation at IBM and semiconductor processing technology at GLOBALFOUNDRIES.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Si2 Compact Model Coalition Releases Vital Updates to Industry Workhorse BSIM-Bulk

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The Si2 Compact Model Coalition has released important updates to the popular BSIM-Bulk standard, a compact SPICE model developed by researchers at the University of California, Berkeley, and supported by developers at the Indian Institute of Technology Kanpur.

Three years in the making, the latest version of BSIM-Bulk offers improved accuracy, convergence and performance over the previous version and various bug fixes. It also features high-voltage transistor modeling, node collapsing, improved flicker noise modeling, and enhanced tuning flexibility in capacitances.

“The new high voltage model provides a good unified solution to low and medium rating of HV-MOS,” said Kaiman Chan of Texas Instruments, chair of the BSIM-Bulk Working Group. “HV-MOS devices are commonly used in radio frequency power amplifiers, power management integrated circuits, and smart power ICs in consumer and automotive applications. BSIM-Bulk’s latest update enables designers to account for unique device phenomena, which are critical for circuit simulation of high-voltage devices.”

To meet the speed requirements of an evolving industry, the latest version of BSIM-Bulk also offers node collapsing, resulting in faster runtime and reduced simulation and design times for modern billion-transistor systems.

The updates also include a revamped flicker noise model, which is relevant to low-noise analog and radio frequency applications. “As the standard method for small-signal flicker noise does not scale to that of large signals, BSIM-Bulk introduced changes for modeling both small and large signal noise accurately,” said Avirup Dasgupta, post-doctoral developer at the University of California, Berkeley. “BSIM-Bulk updates also provide enhanced tuning flexibility of capacitances, increasing accuracy in AC, transient and RF simulation.”

CMC chair Peter Lee praised the group, saying, “These updates add significant breadth and depth to BSIM-Bulk to ensure the model will continue serving the industry for current and future technology generations. The time savings in circuit simulations alone are impressive and provide a meaningful boost to designers.”

The CMC is a collaborative industry group that standardizes SPICE device models. In addition to direct interaction with model developers and priority standing for bug fix and enhancement requests, CMC members receive 18-month advance model access before general release.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Manny Sifakis Named Qualcomm Representative To Si2 OpenAccess Coalition

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Emmanuel (Manny) Sifakis has been named Qualcomm’s representative to the Si2 OpenAccess Coalition.  Manny is currently senior staff engineering manager at Qualcomm, where he leads the CAD IP Quality and Design Management teams.

Manny has more than 15 years of experience in the VLSI field.  His roles have ranged from RTL to GDS delivery of custom and semi-custom designs to CAD flow and infrastructure design and development.

Si2 OpenAccess, the world’s most widely used, open-reference database for IC design, creates authentic interoperability between EDA companies and semiconductor designers and manufacturers.

Si2 Compact Model Coalition Offers Automatic Rule-Checking Software to Members and Developers

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CMC Technical Advisor Geoffrey Coram of Analog Devices has developed and contributed device model rule-enforcing software to Si2. Known as Verilog-A Model Pythonic Rule Enforcer, or VAMPyRE, the software is a standalone compact model parser and checker written in Python.

VAMPyRE checks compact model implementation for a variety of problematic errors, such as hidden-state variables, bias-dependent switch branches, integer division, and unused parameters or variables. VAMPyRE also reviews the style of code, suggesting proper indentation and complaining about extra spaces or tabs. Resolving such errors during development can lead to dramatic time and cost savings during production.

“Commercial simulators generally just run Verilog-A models and are not usually concerned about unused parameters or poor coding style,” Coram said. “But sometimes an ‘unused’ parameter is an indication of an error, because that parameter should have been used in an equation.”  The tool is expected to bring benefits to multiple audiences: model developers want help during code development while EDA vendors would like a consistent coding style to help their optimization. Other CMC members want to verify compliance with the CMC’s Verilog-A Code Standards Policy, which was approved last fall.

CMC Chair Peter Lee agreed. “VAMPyRE is invaluable to enable the development of model code to meet the highest level of quality expected from the models standardized by the CMC. Due to these standard models being widely used in the semiconductor industry, issues with the code can potentially have a large impact to the semiconductor design business. VAMPyRE has already found errors in beta code under development of existing models before release, and we look forward to further improving and enhancing our current and next-generation models with VAMPyRE.”

To encourage widespread adoption, Si2 is offering VAMPyRE to CMC members and model developers under an open-source license.

Si2 Publishes White Paper on Expanding Use of AI/ML in Semiconductor Electronic Design

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A new Silicon Integration Initiative white paper identifies a common data model as the most critical need to accelerate the use of artificial intelligence and machine learning in semiconductor electronic design automation.

The white paper, produced by a 20-member Si2 Special Interest Group, reports on findings of a global survey that identifies planned usage and structural gaps for AI and ML in EDA. It is available at  https://si2.org/product/collaborative-data-model/

Leigh Anne Clevenger, Si2 senior data scientist, said that the white paper identifies “a standard, common model for classifying and structuring machine learning and inference data as being crucial to accelerating the use of AI/ML in EDA. This data model would provide a foundation for addressing the data organization gap for chip developers, EDA tool developers, IP providers, and researchers. It would support design data and derived data for high-interest use cases.”

The survey also identifies a common reference flow, on-line AI/ML courses and organized training data as industry needs.

The white paper addresses:

  • Machine Learning and IC Design
  • Demand for Data
  • Structure of a Data Model
  • A Unified Data Model: Digital and Analog Examples
  • Definition and Characteristics of Derived Data for ML Applications
  • Need for IP Protection
  • Unique Requirements for Inferencing Models
  • Key Analysis Domains
  • Conclusions and Proposed Future Work

Member of the Si2 Special Interest Group include:

  • Advanced Micro Devices
  • Ansys
  • Cadence Design Systems
  • GLOBALFOUNDRIES
  • Hewlett Packard Enterprise
  • IBM
  • Intel Corp.
  • Intento Design
  • Keysight Technologies
  • Mentor, a Siemens Business
  • NC State University
  • PDF Solutions
  • Qualcomm
  • Samsung
  • Sandia National Laboratories
  • Silvaco
  • SK Hynix
  • Synopsys
  • Texas Instruments
  • Thrace Systems

 

Rahul Goyal of Intel Re-elected Board Chair of Silicon Integration Initiative

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AUSTIN, Texas — Rahul Goyal, vice president and director of R&D strategic enablement at Intel, has been re-elected to a one-year term as chairman of the board of directors of Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

Besides Intel, other companies represented on the Si2 board are: Ansys, Cadence Design Systems, GLOBALFOUNDRIES, Google, IBM, Mentor-a Siemens Business, Qualcomm Technologies, Samsung, Synopsys and Texas Instruments.

John Ellis, Si2 president and CEO, said Goyal’s re-election “provides sustained leadership as we continue to advance with our members into artificial intelligence and machine learning, 5G, and autonomous vehicles, as well as assure continuity and stability during the disruption that COVID has inflicted on our industry.”

Goyal has global responsibility at Intel for strategic sourcing, supply chain strategy, strategic collaborations, ecosystem enablement, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Si2 Announces 2020 Power of Partnerships Award Winners

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AUSTIN, Texas – Semiconductor design experts from industry and academia are this year’s winners of the Silicon Integration Initiative’s Power of Partnerships Award, recognizing the Si2 team that has made the most significant contributions to the field of electronic design automation.

Led by Jerry Frenkil, Si2 director of OpenStandards, members of the Unified Power Model Working Group are being honored for developing Si2 UPM, a system-level power modeling standard which helps designers describe, analyze, and control power consumption, critical factors in reducing overall design costs and increasing chip performance.

Honorees from the UPM Working Group are:

  • Nagu Dhanwada, senior technical staff member, IBM, Working Group Chair
  • Allen Baker, lead software developer, Ansys
  • Daniel Cross, principal solutions engineer, Cadence Design Systems
  • Rhett Davis, professor of Electrical and Computer Engineering, NC State University
  • David Ratchkov, founder and CEO, Thrace Systems

UPM was created under the auspices of the OpenStandards Coalition, a technology incubator developing critical enabling technologies for fast-track industry approval toward standardization. Frenkil said the working group “has pioneered new methods for power modeling and analysis, leading to increased power efficiency. This has created new opportunities for system architects, SoC designers, IP providers, and EDA developers to estimate and control power consumption, especially at the system level.”

UPM led directly to the creation of the IEEE Standard for Power Modeling to Enable System Level Analysis, or IEEE 2416-2019. This standard is based almost entirely on the efforts of the UPM working group.

Each Si2 coalition nominates one team for the annual Power of Partnerships award, which spotlights the essential role volunteers from Si2 member companies play in Si2’s continuing success and value to the industry. The Si2 board of directors selects the winners.

Runners up for 2020 are:

Compact Model Coalition, Open Model Interface Working Group
Chair, Colin Shaw, Silvaco

Contributed to Si2 initially by Taiwan Semiconductor Manufacturing Company, OMI is built around the TSMC Model Interface. OMI allows circuit designers to simulate and analyze such significant physical effects as self-heating and aging, and to perform extended design optimizations, including statistical modeling of process variations.

OpenAccess Coalition, Polygon Operators Working Group
Chair, James Masters, Intel

The Polygon Operators Working Group develops oaxPop, an API extension used with Si2 OpenAccess, the world’s most widely used open reference database for IC design. Originally contributed to Si2 by Intel, oaxPop brings the power of the popular Boost Polygon Library into the expanding OpenAccess design database ecosystem.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Executives from Siemens, Qualcomm and Samsung Join Si2 Board of Directors

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AUSTIN, Texas—Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for semiconductor design tools, announced today the election of its 2020-2021 board of directors.

Joining the Si2 board this year are:

  • Juan C. Rey, vice president of Engineering, Mentor, a Siemens Business
  • Pankaj Kukkal, vice president, EDA, Emulation and Post-Silicon Engineering, Qualcomm Technologies
  • Jung Yun Choi, corporate vice president, Electronics Design Technology, Samsung Electronics

Re-elected board members are:

  • Vic Kulkarni, vice president and chief strategist, Ansys
  • Stanley Krolikoski, fellow, Ecosystems, Cadence Design Systems
  • Richard Trihy, vice president, Design Enablement, GLOBALFOUNDRIES
  • Roger Carpenter, hardware engineer, Google
  • Leon Stok, vice president, Electronic Design Automation Technologies, IBM
  • Rahul Goyal, vice president, Intel Corp., director, R&D Strategic Enablement
  • David DeMaria, corporate vice president, Strategic Initiatives and Market Intelligence, Synopsys
  • Keith Green, distinguished member of the technical staff, Texas Instruments

The Si2 board represents leading semiconductor manufacturers and foundries, fabless companies and EDA software providers.  Si2’s key programs include: OpenAccess—a standard application programming interface and reference source code for the design database used by all major chip design software suppliers; and the Compact Model Coalition, which selects and supports industry-standard SPICE simulation models.

About Si2

Founded in 1988, Si2 provides standard interoperability solutions for semiconductor design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Jeff Brubaker of Synopsys Joins Si2 OpenAccess Change Team

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Jeff Brubaker, infrastructure architect for Custom Compiler at Synopsys, has been elected to the Si2 OpenAccess Change Team. OpenAccess, the world’s most widely used, open-reference database for IC design, creates authentic interoperability between EDA companies and semiconductor designers and manufacturers.

Jeff started working on custom design tools at Avanti in 2000 and joined Synopsys in 2002. In 2004, he was on the Synopsys team which started the product that eventually became Custom Compiler–the Synopsys design environment for full-custom analog, custom digital, and mixed-signal IC design. He has worked with OpenAccess since 2005 and currently manages the Synopsys team responsible for OpenAccess-related development and maintenance.