Si2 Compact Model Coalition Releases Vital Updates to Industry Workhorse BSIM-Bulk

The Si2 Compact Model Coalition has released important updates to the popular BSIM-Bulk standard, a compact SPICE model developed by researchers at the University of California, Berkeley, and supported by developers at the Indian Institute of Technology Kanpur.

Three years in the making, the latest version of BSIM-Bulk offers improved accuracy, convergence and performance over the previous version and various bug fixes. It also features high-voltage transistor modeling, node collapsing, improved flicker noise modeling, and enhanced tuning flexibility in capacitances.

“The new high voltage model provides a good unified solution to low and medium rating of HV-MOS,” said Kaiman Chan of Texas Instruments, chair of the BSIM-Bulk Working Group. “HV-MOS devices are commonly used in radio frequency power amplifiers, power management integrated circuits, and smart power ICs in consumer and automotive applications. BSIM-Bulk’s latest update enables designers to account for unique device phenomena, which are critical for circuit simulation of high-voltage devices.”

To meet the speed requirements of an evolving industry, the latest version of BSIM-Bulk also offers node collapsing, resulting in faster runtime and reduced simulation and design times for modern billion-transistor systems.

The updates also include a revamped flicker noise model, which is relevant to low-noise analog and radio frequency applications. “As the standard method for small-signal flicker noise does not scale to that of large signals, BSIM-Bulk introduced changes for modeling both small and large signal noise accurately,” said Avirup Dasgupta, post-doctoral developer at the University of California, Berkeley. “BSIM-Bulk updates also provide enhanced tuning flexibility of capacitances, increasing accuracy in AC, transient and RF simulation.”

CMC chair Peter Lee praised the group, saying, “These updates add significant breadth and depth to BSIM-Bulk to ensure the model will continue serving the industry for current and future technology generations. The time savings in circuit simulations alone are impressive and provide a meaningful boost to designers.”

The CMC is a collaborative industry group that standardizes SPICE device models. In addition to direct interaction with model developers and priority standing for bug fix and enhancement requests, CMC members receive 18-month advance model access before general release.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Manny Sifakis Named Qualcomm Representative To Si2 OpenAccess Coalition

Emmanuel (Manny) Sifakis has been named Qualcomm’s representative to the Si2 OpenAccess Coalition.  Manny is currently senior staff engineering manager at Qualcomm, where he leads the CAD IP Quality and Design Management teams.

Manny has more than 15 years of experience in the VLSI field.  His roles have ranged from RTL to GDS delivery of custom and semi-custom designs to CAD flow and infrastructure design and development.

Si2 OpenAccess, the world’s most widely used, open-reference database for IC design, creates authentic interoperability between EDA companies and semiconductor designers and manufacturers.

Si2 Compact Model Coalition Offers Automatic Rule-Checking Software to Members and Developers

CMC Technical Advisor Geoffrey Coram of Analog Devices has developed and contributed device model rule-enforcing software to Si2. Known as Verilog-A Model Pythonic Rule Enforcer, or VAMPyRE, the software is a standalone compact model parser and checker written in Python.

VAMPyRE checks compact model implementation for a variety of problematic errors, such as hidden-state variables, bias-dependent switch branches, integer division, and unused parameters or variables. VAMPyRE also reviews the style of code, suggesting proper indentation and complaining about extra spaces or tabs. Resolving such errors during development can lead to dramatic time and cost savings during production.

“Commercial simulators generally just run Verilog-A models and are not usually concerned about unused parameters or poor coding style,” Coram said. “But sometimes an ‘unused’ parameter is an indication of an error, because that parameter should have been used in an equation.”  The tool is expected to bring benefits to multiple audiences: model developers want help during code development while EDA vendors would like a consistent coding style to help their optimization. Other CMC members want to verify compliance with the CMC’s Verilog-A Code Standards Policy, which was approved last fall.

CMC Chair Peter Lee agreed. “VAMPyRE is invaluable to enable the development of model code to meet the highest level of quality expected from the models standardized by the CMC. Due to these standard models being widely used in the semiconductor industry, issues with the code can potentially have a large impact to the semiconductor design business. VAMPyRE has already found errors in beta code under development of existing models before release, and we look forward to further improving and enhancing our current and next-generation models with VAMPyRE.”

To encourage widespread adoption, Si2 is offering VAMPyRE to CMC members and model developers under an open-source license.

Si2 Publishes White Paper on Expanding Use of AI/ML in Semiconductor Electronic Design

A new Silicon Integration Initiative white paper identifies a common data model as the most critical need to accelerate the use of artificial intelligence and machine learning in semiconductor electronic design automation.

The white paper, produced by a 20-member Si2 Special Interest Group, reports on findings of a global survey that identifies planned usage and structural gaps for AI and ML in EDA. It is available at

Leigh Anne Clevenger, Si2 senior data scientist, said that the white paper identifies “a standard, common model for classifying and structuring machine learning and inference data as being crucial to accelerating the use of AI/ML in EDA. This data model would provide a foundation for addressing the data organization gap for chip developers, EDA tool developers, IP providers, and researchers. It would support design data and derived data for high-interest use cases.”

The survey also identifies a common reference flow, on-line AI/ML courses and organized training data as industry needs.

The white paper addresses:

  • Machine Learning and IC Design
  • Demand for Data
  • Structure of a Data Model
  • A Unified Data Model: Digital and Analog Examples
  • Definition and Characteristics of Derived Data for ML Applications
  • Need for IP Protection
  • Unique Requirements for Inferencing Models
  • Key Analysis Domains
  • Conclusions and Proposed Future Work

Member of the Si2 Special Interest Group include:

  • Advanced Micro Devices
  • Ansys
  • Cadence Design Systems
  • Hewlett Packard Enterprise
  • IBM
  • Intel Corp.
  • Intento Design
  • Keysight Technologies
  • Mentor, a Siemens Business
  • NC State University
  • PDF Solutions
  • Qualcomm
  • Samsung
  • Sandia National Laboratories
  • Silvaco
  • SK Hynix
  • Synopsys
  • Texas Instruments
  • Thrace Systems