SI2 OpenAccess Workshop Presentations

New Directions at Si2

Rob Aslett
President and CEO






Building Powerful Applications
With OpenAccess Extension


James Masters
Principal Engineer

JSON2oa and oa2JSON

Jeff Wilson
EDA Developer

Color Shifting and oaxColor 2.0

Ben Hoefer

Senior EDA Tools Software Engineer

Making OpenAccess Easier to Use

Chris Falkowski
Senior Software Engineer

Introducing Causeway, the New Si2 Member Portal

Lindsay Adamson
Omnia Digital Solutions

Board of Directors 2023 Nominees

2023 Member Meeting Ad

POP Final Rules 2023

PoP Award Instructions

2023 Board Nomination Instructions

By Laws May 15 2023

Ansys Engineer Recognized for Efforts to Develop Secure API for EDA AI/ML Data

Akhilesh Kumar, principal research and development engineer at Ansys, has received the quarterly Silicon Integration Initiative Pinnacle Award, which recognizes volunteers for their contributions to Si2’s success as a research and development joint venture for semiconductor design automation software.

Kumar was honored for his contributions to advancing a standard application programming interface for accessing processed data from EDA tools and databases. This interface, known as the Secure ProcEssEd Data (SPEED) API, will help enable secure and uniform access to data needed to develop, train, and implement artificial intelligence and machine learning engines that accelerate chip design processes.

“EDA tools typically offer access to their design data via our OpenAccess database and API,” said Leigh Anne Clevenger, Si2 vice president of technology. “However, until now, there has not been a standard API for the processed data these tools output. As a result, users often need to create various extraction and translation scripts to convert the data into a suitable format for AI/ML training. This process is often time-consuming and error-prone, as any changes to the output file parameters or formats can break translation scripts and disrupt access to legacy training data.”

Si2’s AI/ML Special Interest Group conducted a survey identifying key obstacles to using AI/ML for advanced electronic design. The results indicated a need for a standard API for processed data and that the limited availability of training data for AI/ML models hindered significant progress in this field.

John Ellis, Si2 president and CEO, stated, “The electronics industry is facing a number of challenges, including a rapid increase in design complexity and a growing shortage of skilled talent for next-generation system design. To overcome these issues, we need to optimize current design processes and create new AI-powered tools to help navigate the complex tradeoffs necessary for optimizing system-level designs. These tools are essential to helping us understand and address the increasing complexity of designing advanced electronic systems. SPEED API is a key missing building block and its adoption will help accelerate the development of AI/ML-enhanced design flows.”

Ellis also praised Kumar’s contributions to the SPEED API project, stating, “Akhilesh has been a great catalyst for driving the SPEED API effort forward. He brings a wealth of industry experience and encourages new ideas and strategies, fostering a sense of ownership among group members. His award is well-deserved, and I’m excited to see the impact of the SPEED API under his leadership.”

Kumar’s R&D focus at Ansys is on EDA reliability solutions, including electrothermal, thermal, electrostatic discharge, and substrate noise analysis applications. His research interests are ML and algorithmic techniques for EDA solutions. He has published papers in top conferences and journals within the broad area of EDA and worked on several AI/ML projects involving multiple EDA tools with complex data interfaces and models.

Kumar previously served as a design engineer at STMicroelectronics, working on behavioral, timing, and power models for memories and memory controllers. He received his Ph.D. and M.S. in electrical and computer engineering from the University of Waterloo and a Bachelor of Technology in electrical engineering from the Indian Institute of Technology, Roorkee.

Geoffrey Coram of Analog Devices Wins Si2 Pinnacle Award

Geoffrey Coram, staff CAD engineer at Analog Devices, has received the quarterly Silicon Integration Initiative Pinnacle Award, recognizing volunteers for their exceptional contributions to Si2’s success as a leading semiconductor research and development joint venture.

Coram serves as chair of three working groups within the Si2 Compact Model Coalition, which pools industry resources to fund the development of standard compact SPICE models and interfaces promoting simulation tool interoperability. In 2016, he was named CMC Technical Advisor for Verilog-A Code Quality. Coram has a long history with Verilog-A, having led the Accellera Verilog-AMS subcommittee’s work for adding compact modeling extensions in Language Reference Manual version 2.2, released in 2004.

He recently developed and released an open-source tool for checking Verilog-A models for common errors and performance issues in 2020. The tool, known as the Verilog-A Model Pythonic Rule Enforcer, or VAMPyRE, has seen rapid industry adoption since its launch. He also has reviewed the Verilog-A implementation of every CMC standard model. In 2020, Coram was recognized by the University of California at Berkeley’s BSIM model team as “Guardian of Verilog-A Compact Models for the Global Semiconductor Industry.”

“Geoffrey is an innovative voice within the CMC and has an excellent critical eye,” said John Ellis, president and CEO of Si2. “His work with VAMPyRE illustrates his longstanding commitment to efficiency and interoperability. We are fortunate to have him in leadership.”

Coram joined Analog Devices in 2000 and focuses on its internal circuit simulator and other internal CAD tools. He earned his Ph.D. in electrical engineering from the Massachusetts Institute of Technology with a thesis on thermodynamics and noise modeling in circuits.

Mark Rossman Elected Architect of SI2 OpenAccess Change Team

Mark Rossman, software engineering group director at Cadence Design Systems, is the new architect of the Si2 OpenAccess Change Team, the approving body for changes to the OpenAccess API and reference database implementation. He replaces Michaela Guiney, also from Cadence, who retired in December.

Rossman has spent over 40 years in electronic design automation, developing software algorithms for automatic routing and layout migration capabilities. During the past 20 years at Cadence, he developed routing flows and solution integration for the Virtuoso Platform and organized collaboration between internal groups and key external development partners.

Before the Virtuoso Platform development, he worked on the CCT Cadence Chip Assembly Router routing tools and Catena’s Space Based Routing Technologies. He has five patents granted for routing and layout migration algorithms.

Marshall Tiner, Si2 senior director of OpenAccess, said Rossman “brings extensive experience in routing, layout, and design rule technologies as well as large scale multi-threaded development and collaborative integration. His on-the-job experience with OpenAccess, brings an important perspective to the OpenAccess Coalition.”

About the Silicon Integration Initiative

Si2 is a leading R&D joint venture that provides standard interoperability solutions for IC design tools. Its primary programs include CMC and OpenAccess, the world’s most widely used open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.