Qualcomm Executive Joins Si2 Board of Directors

Pankaj Kukkal, vice president of Engineering at Qualcomm Inc., has been elected to the Silicon Integration Initiative board of directors. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

In his current role, Kukkal oversees all EDA, emulation and post-silicon engineering functions for mobile, compute, automotive, and artificial intelligence/machine learning business units. He joined Qualcomm in 2012. He has contributed to delivering over 50 leading-edge SoCs in various application domains.

Kukkal has more than 25 years of experience in EDA, silicon, systems, and software engineering. Before joining Qualcomm, he held various leadership positions at Intel, focusing on CAD, emulation and validation. He has led the creation of several industry-leading technologies for chip design, emulation and post-silicon debug and automation.

Kukkal has a bachelor’s degree in electrical engineering from the National Institutes of Technology, India, and a master’s degree in computer engineering from the University of South Carolina.

John Ellis, president and CEO, said Kukkal brings crucial experience and domain knowledge to the Si2 board.  “Pankaj has been in key, strategic roles at Qualcomm and Intel over his long career. The insights he has gained, along with his extensive network of contacts including former associates, customers and suppliers in the semiconductor industry, will be invaluable as Si2 and its board maps out where the industry is going, and what Si2 members need from us to help propel them there most efficiently.”

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.


Si2 Compact Model Coalition Releases BSIM-CMG SPICE Model for Advanced IC Designs

CMC Members Benefit from 18-Month Early Access to New Standard Model

AUSTIN, Texas — The Si2 Compact Model Coalition has released the latest version of BSIM-CMG FinFET, a standard compact SPICE model developed by researchers at the University of California, Berkeley, in conjunction with 20 partners from many of the industry’s leading semiconductor companies.

CMC is a collaborative industry group that standardizes SPICE (Simulation Program with Integration Circuit Emphasis) device models.

John Ellis, Si2 president and CEO, said FinFET is the transistor design that powers the industry along Moore’s Law to advanced leading-edge integrated circuits, including the latest 7nm chips used in every new smartphone, tablet, server, and personal computer. “The industry-standard SPICE model for FinFET is the 3D multi-gate transistor, a critical part of the ecosystem. Its sophistication required a cross-industry team to bring this model to fruition,” Ellis said.

“FinFET” refers to a visual description of a multi-gate, non-planar transistor. In IC design, field-effect-transistor gates wrap around the three sides of a vertical, fin-like channel, creating conducting channels on all sides of the structure. FinFET was named by Dr. Chenming Hu, a National Medal of Technology and Innovation recipient and professor emeritus in the Electronic Engineering and Computer Science Department at UC Berkeley.

“The model updates in the new release (111.0.0) are important refinements and fixes,” stated CMC BSIM-CMG working group chair, Richard Williams. “This new release will benefit all BSIM-CMG users in its myriad applications.” Through the CMC—­and working under Si2’s anti-trust umbrella as a collaborative R&D joint venture—university researchers, simulation software suppliers, fabless, foundry and integrated device manufacturers team up to produce a variety of industry-standard models. CMC members have immediate access to new standards, while new standards are released to the public 18 months after initial release.

Dr. Harshit Agarwal, a post-doctoral developer at UC Berkeley states, “CMC provides a tie to the industry that keeps us in close touch with the customer’s needs. Without CMC there’s no shared funding to support our model standardization, and the data, testing, and feedback on model performance would have to be sought after on a company-by-company basis. Together we are all much more intelligent and customers can cooperatively prioritize their requested features and bug fixes. Beyond this, the quality assurance program provided by CMC ensures our model, and the simulator provider’s implementations, perform at their absolute best for the designers.”

Dr. Peter Lee, CMC chair, agreed and added, “It has been two-and-a-half years since the last major BSIM-CMG update, which is equivalent to a semiconductor generation or two. This new version implements 25 enhancements and 13 bug fixes which improve accuracy, convergence, and performance when compared to the previous version. These changes can have important implications in shortening design time and ensuring first silicon success for a wide variety of products.”

Enhancements include improvements to the thermal noise model and the introduction of gate current scaling factors. Bug fixes include corrected parameter range, and use of macros instead “ifdef’s”, making the code even more robust.


About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Si2 Elects Board Members for 2019-2020

Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools, announced today the election of the 2019-2020 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference, June 3, 4:00 – 5:30 p.m., Las Vegas Westgate Hotel, Ballroom F.

Joining the Si2 Board this year is:

  • ANSYS—Vic Kulkarni, vice president and Chief Strategist, ANSYS Inc.

Re-elected board members are:

  • Cadence Design Systems—Stanley Krolikoski, fellow, Strategic Alliances
  • GLOBALFOUNDRIES—Richard Trihy, vice president, Design Enablement
  • Google—Roger Carpenter, Hardware Engineer
  • IBM—Leon Stok, vice president, Electronic Design Automation Technologies
  • Intel—Rahul Goyal, vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling
  • Mentor, a Siemens Business—Mick Tegethoff, director of Product Marketing for Analog/Mixed-Signal/RF IC Verification Solutions
  • Qualcomm Technologies—Udi Landen, vice president of Engineering
  • Samsung Electronics—Seungbum Ko, vice president, Electronics Design Technology Team
  • Synopsys—David DeMaria, vice president, Corporate Marketing
  • Texas Instruments—Keith Green, distinguished member of the technical staff, Analog Technology Development

Details on the Si2 Member Meeting and Reception and other Si2 DAC activities are available at https://si2.org/dac_2019/

Si2 Announces Winners of Inaugural Power of Partnerships Awards

Si2 Announces Winners of Inaugural Power of Partnerships Awards

Engineers from Intel, Samsung and Synopsys Honored

AUSTIN, Texas – Semiconductor design experts from Intel, Samsung and Synopsys are winners of the first annual Si2 Power of Partnerships award which recognizes the Si2 group or committee that has made the most significant contributions to the success of electronic design automation industry.

Volunteers of the Si2 OpenAccess oaScript Working Group were the winners of a competition between committees from each of three Si2 coalitions:  OpenAccess, Compact Model, and OpenStandards.  Key contributors from the oaScript Working Group will be recognized during the Si2 Annual Member Meeting Reception at the Design Automation Conference in Las Vegas, Monday, June 3, 4:00 – 5:30 p.m. Las Vegas Westgate Hotel, Ballroom F.

Honorees from the oaScript Working Group are:

  • Rudy Albachten, oaScript Working Group Chair; Co-Chair, OpenAccess Coalition; and Principal Member of the Technical Staff, Intel
  • James D. Masters, Engineering Manager, Intel
  • Cory Krug, Senior Staff Engineer, Samsung
  • Christian Delbaere, Senior Staff Research and Development Engineer, Synopsys

Marshall Tiner, Si2 director of Production Standards, said the oaScript Working Group plays a major role in expanding the functionality of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. “This group has brought EDA development capabilities directly to the designers. EDA startups and design groups within end-user companies use it for rapid development of production design tools that strengthen OpenAccess’ relevance,” Tiner said.

“The use of scripting languages, such as Python, to directly access the OpenAccess database is a powerful feature. Turn-around time for creating and modifying scripted code is very fast, and almost all new university graduates are well-versed in one or more scripting languages. Beyond this, there are a number of additional packages available, such as the powerful Polygon Operators extension which relies on oaScript. Access to AI tools, such as TensorFlow, which is built on Python, is now accessible to our users,” Tiner added.

Each Si2 coalition nominated one team for the inaugural award, which spotlights the essential role that teams and individual member volunteers play in Si2’s continuing success:

Runners up in 2019 were:

Compact Model Coalition:  Gallium Nitride High Electron Mobility Transistor (HEMT) Model Working Group, which released two standard models in 2018, culminating a multi-year effort by members and developers.

OpenStandards Coalition:  Unified Power Model Working Group developed several versions of a specification for system-level power modeling focused on IP blocks of arbitrary complexity.

James Masters of Intel to Lead Si2 Extensions Steering Group

AUSTIN, Texas — James Masters of Intel has been elected chairman of the Silicon Integration Initiative Extensions Steering Group, a team of industry volunteers that creates productivity enhancements to OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

The ESG was launched in 2011 to increase the ease and pace of adding OpenAccess functionality, through extensions to the database, without affecting the consistency and stability of the core API standard and its associated reference implementation.

Marshall Tiner, Si2 director of Production Standards, said the ESG is responsible for reviewing and approving new features and capabilities for the API which are not part of the regular development process. “This has allowed for more flexible development in the OpenAccess environment to meet ever-changing market requirements,” Tiner said.

“James has played a major role in the ESG since its creation. His work with Si2 is an example of his decade-long advocacy for standards to streamline the design flow and maximize productivity and reuse,” Tiner added. “That includes guidance developing the ESG’s major subgroups, oaScript and oaxPop. oaScript provides scripting-language access into the database for Python, tcl, Ruby, and perl, allowing rapid development of user-created tools. oaxPop is the polygon operators extension that makes use of oaScript to provide a Python-based, rapid polygon analysis package for users.”

A 23-year Intel veteran, Masters currently manages an Intel team that enables custom layout capabilities of process nodes, including development of process design kit content. He works with EDA suppliers to improve the overall custom layout of the EDA ecosystem.

Si2 Names Dr. Rhett Davis Technical and Education Advisor

AUSTIN, Texas — Rhett Davis, professor of Electrical and Computer Engineering at North Carolina State University, has been named Technical and Educational Advisor for Silicon Integration Initiative. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

“This new position expands Davis’ reach and impact on the semiconductor industry,” said John Ellis, Si2 president and CEO.  “His experience with the Si2 OpenAccess database and in artificial intelligence and machine learning will be brought to bear on expanding the ecosystem surrounding our newly upgraded version of OA. The new OA release will greater support high-performance, partitioned, multithreaded AI EDA applications. Dr. Davis’ expertise will assist Si2 and its members in bridging the gap between visionary research and real-world, high-performance, AI applications.”

In this expanded advisory role Davis, who has a doctorate in electrical engineering from the University of California at Berkeley, will continue consulting for Si2 in the areas of system-level power modeling and compact modeling. He has been instrumental in prototyping early-stage implementation of the newly created Unified Power Model now being standardized by Si2 within IEEE.  In the Si2 Compact Model Coalition, Davis has helped the Open Model Interface Working Group rearchitect the TSMC-contributed interface, which allows users to modify model parameters during circuit simulation.

Davis will also support the five university members of the OpenAccess Coalition: North Carolina State, University of Florida, State University of New York, Stanford University and Einhoven University of Technology (Netherlands.)  University members have direct use of the OpenAccess database, which streamlines the path to developing design production tools.

Dr. Davis joined North Carolina State University in 2002 as an assistant professor and became professor in 2008. He received the National Science Foundation Faculty Early Career Development award in 2007 and the Si2 Distinguished Service Award in 2012 development of standards for electronic design automation, and the FreePDK open-source, predictive process design kit.

He has been an IEEE member since 1993 and became a senior member in 2011. He has published over 50 scholarly journal and conference articles

Dr. Davis’ research is centered on developing methodologies, CAD tools, and circuits for systems-on-chip in emerging technologies. His interests include 3DIC design and low-power and high-performance circuit design for digital signal-processing and embedded systems.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. Its activities include support of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws

Dr. Leigh Anne Clevenger Joins Si2 Technical Team

Machine Learning Expert Will Bolster Collaborative R&D Programs

Dr. Leigh Anne Clevenger, a professional software engineer with over 15 years’ experience at IBM and GlobalFoundries, has joined Si2 as a principal software design engineer.

With domain knowledge ranging from circuit simulation to data science, Dr. Clevenger will initially focus her expertise on accelerating the Si2 OpenStandards Coalition standardization efforts in machine learning and system-level power modeling.

Dr. Clevenger, who earned her doctorate in Software Engineering and Machine Learning at Pace University, has extensive experience in semiconductor design automation and semiconductor processing technology.  She is a published expert in detailed circuit simulator systems, including IBM PowerSPICE, Cadence Spectre/APS/XPS/Ultrasim, and Synopsys HSPICE.  At GlobalFoundries she was a software development engineer for automotive and gaming computer chips.

“Dr. Clevenger is known for driving business success through establishing collaboration and dialogue between all sectors of the electronic design automation and semiconductor communities,” said John Ellis, Si2 president and CEO.  “Her expertise in machine learning will be especially valuable to Si2 members who increasingly utilize that science to gain insights from data to improve the quality and efficiency of production and decision software systems.”

Dr. Clevenger has published and presented research on data science, including big data analytics, machine learning algorithms, and wearable computing.  She has filed over 30 patents in the areas of health care and fitness based on Internet of Things sensors, improving engagement with virtual and augmented reality and semiconductor innovations. For her doctorate, she developed a machine learning system for active screening of cardiac patients.


IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard

Si2 has announced  that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly in to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

Simplified Power Modeling

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models.  P2416 is scheduled for balloting in early 2019.

Industry Contributions

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods.  “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM.  “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard.  Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

Ready for P2416 Balloting

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project.  “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization.  We anticipate going to ballot early next year.”

For more information about this project, contact Jerry Frenkil at jfrenkil@si2.org.  For information about the Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.

Si2 Launches Effort to Standardize New IC Design Language

Silicon Integration Initiative Inc. (Si2), a research and development joint venture providing standard interoperability solutions for IC design tools, has launched a working group to standardize a new, formal declarative language that greatly simplifies finding and correcting design flaws in complex, leading-edge chip designs early in a design flow. Named OPAL (Open Pattern Analysis for Layout), […]