The demand for increased power efficiency in both wired and wireless applications continues to grow unabated. This demand has generated considerable interest in low power design methods that have become well established at the RTL, gate, and physical, levels. While it’s accepted that opportunities for reducing power at the system level are high, low power design automation at the system level has lagged. One primary reason for that lag has been a lack of system-level IP block power models, particularly of standardized, inter-operable, models. This has in turn motivated the development of Unified Power Models (UPM), recently standardized as IEEE 2416-2019.

This is the first tutorial since the standard’s release in summer 2019. It addresses how this new modeling technology is used and the novel, related tools and methodology it enables. This new standard was developed to meet the power modeling needs of three distinct groups of users: IP providers and model producers, system architects and SoC designers, and EDA developers. UPM/2416’s rich semantics facilitate easy and interoperable model exchange by providing four different data representations – scalars, tables, expressions, and contributors (process, voltage, and temperature-independent proxies for energy and power)– and three different modeling levels – bit, system, and multi-level. UPM/2416 models also facilitate efficient electro-thermal analysis by providing voltage and temperature independent modeling enabling the late-binding of voltage and temperature values at analysis run time. The tutorial will begin with an overview of the standard.