Committee Corner: Aparna Dey, Cadence Design Systems
Aparna Dey chairs the Si2 Low Power Working Group and represents Cadence Design Systems in other Si2 activities and industry standards organizations. She also chairs the IEEE Electronic Design Symposium, an annual conference held in Monterey, Calif., and is the treasurer for IEEE Design Automation Standards Committee.
As the technical marketing group director in the Cadence Standards Group, Dey has focused on standards since 2012. It’s a role she finds both interesting and challenging. “It’s exciting and rewarding to work together in the standards committee with our industry peers, including our competitors and customers, on interoperability solutions. However, showing our technical leadership while being mindful of what we contribute is a balancing act at times.”
Her 14 years at Cadence includes various engineering, methodology services, and technical marketing positions. She led the ASIC Alliances and SOC/IP Reuse Group in the Alliances and Methodology Services Division. That background provides a good match for her current role. “Working with R&D architects to determine which standards are useful to which products requires broad exposure to all our marketing efforts.”
One side benefit to her current role is a reduced travel schedule, allowing her to spend more time with her third-grade daughter. “She loves math and science and hopes to be an engineer.”
Dey holds a Bachelor of Engineering degree in Electronics and Telecommunication from Netaji Subhas Institute of Technology, University of Delhi, India.