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Compact Model Coalition
Industry Cost-Savings through Standard Models

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The Compact Model Coalition (CMC) is a working collaborative group focused on the standardization of SPICE (Simulation Program with Integration Circuit Emphasis) device models.

When a new or enhanced chip is designed, it must be simulated prior to manufacturing. This can be thought of as proof of concept and is vitally important to validate the concept before it enters the capital intensive phase of manufacturing. The simulations are based on standard models (expressed in the form of equations) governed by CMC.

Once the standard models are proven and accepted by CMC, they are incorporated into design tools widely used by the semiconductor industry. The equations at work in the standard models setting process are developed, refined and maintained by leading universities the CMC directs and funds to standardize and improve the models.

The members of our coalition are modeling experts. All join the CMC for an important and highly valuable reason: they want to be a voice, an influencer, for themselves and their companies in the standard-model- setting process.

While anyone in the industry can access CMC open source standards and models, CMC members enjoy a layer of additional benefits:

  • Early access to new solutions. CMC members can access new simulation models and existing model enhancements long before they are released to the public.
  • A voice in the selection process. Members determine which models the CMC targets for new development and which models receive ongoing CMC financial support.
  • Professional growth. CMC members enjoy the opportunity to learn from and work with the world’s most talented compact model developers from both industry and academia.

CMC Standard Compact Model Developers

Powering Simulations that Power the Electronics World

The University of California, Berkeley: BSIM Bulk, BSIM-SOI, BSIM-CMG, and BSIM-IMG

Dr. Chenming Hu

Chenming Calvin Hu is Distinguished Professor of Microelectronics at University of California, Berkeley. From 2001-2004, he was the Chief Technology Officer of TSMC, world’s largest IC foundry. IEEE, the world’s largest technical association, called him “microelectronics visionary” whose seminal work on metal-oxide semiconductor MOS reliability and device modeling has had enormous impact on the continued scaling of electronic devices”. He is a member of the US National Academy of Engineering, the Chinese Academy of Sciences, and Academia Sinica.

University of Hiroshima: HiSIM2, HiSIM HV, HiSIM SOI, and HiSIM SOTB

Dr. Mitiko Miura-Mattausch

Since 1996, Mitiko Miura-Mattausch has been a Professor at the Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima University, where she leads the Ultra Scaled Devices Laboratory. From 1981 to 1984, she was a Researcher at the Max-Planck Institute for Solid-State Physics, Stuttgart, Germany. From 1984 to 1996, she was with the Corporate Research and Development, Siemens AG, Munich, Germany, working on hot electron problems in MOSFETs, the development of bipolar transistors, and analytical modeling of deep sub-micrometer MOSFETs for circuit simulation. She has more than 300 publications and three books, is an IEEE fellow since 2001, and was honored by several awards.

University of California, San Diego: HICUM/L2, HICUM/L0

Dr. Michael Schröter

Dr. Schröter is a Research Professor at The University of California, San Diego, and also has been appointed as Full Professor at the University of Technology at Dresden (TUD). He has more than 25 years of experience in the semiconductor industry focusing on device modeling and design as well as simulation and experimental high-frequency characterization, leading efforts at Rockwell, Nortel, Bell Northern, and Ruhr-University Ruhr-University. He has served on Technical Advisory Boards for RF Nano Corp, and RF Magic, Inc , and co-founded XMOD Technologies. Dr. Schröter currently serves as the Technical Program Manager of DOTFIVE, a large European Research project on next generation SiGe HBT technology.

Auburn University: MEXTRAM

Dr. Guofu Niu

Dr. Niu has been a Full Professor at Auburn University in the department of electrical and computer engineering since 2004. His research and teaching activities include SiGe devices, RF CMOS, high-frequency on-chip characterization, noise, radiation effects, low temperature electronics, compact modeling and TCAD. He has published over 100 journal papers and over 100 conference papers, and is the co-author of the book Silicon-Germanium Heterojunction Bipolar Transistors, Artech House, 2003 (with John Cressler), and many book chapters. Dr. Niu serves as an Editor of IEEE Transactions on Electron Devices.

CEA-Leti: PSP, L-UTSOI

Dr. Thierry Poiroux, Dr. Olivier Rozeau

Dr. Poiroux is the Head of the Simulation and Compact Model Laboratory at CEA-Leti. In this role, he leads a team devoted to the modeling and simulation for microelectronics processes and devices. The Lab’s activities cover atomistic simulation, TCAD, multiphysics simulation and SPICE modeling. Personal background: advanced CMOS device development, compact model of transistors.

Dr. Rozeau is a researcher at CEA-Leti in the Simulation and Compact Model Laboratory. He received the Ph.D. degree from Grenoble INP France in 2000. He has more than 20 years of experience in device compact modeling and characterization. He is developer of industry standard PSP model for bulk MOSFETs and Leti-UTSOI for FDSOI MOSFETs. His other research interests in modeling are advanced multigate MOSFET and photonic devices.

Massachusetts Institute of Technology: MVSG-MIT, MVSG_CMC

Dr. Ujwal Radhakrishna

Dr. Radhakrishna is postdoctoral research associate in the Research Laboratory of Electronics (RLE) at MIT working in the area of energy harvesting. It involves the design of MEMS based harvesters and low power circuit design for machine health monitoring. He received his Ph.D from Microsystems Technology Laboratory (MTL) at MIT in 2016. His dissertation involved developing physics-based compact model for Gallium Nitride (GaN) high electron mobility transistors (HEMTs) for RF and HV applications. He received his Master of Science in Electrical engineering at MIT in 2013 and B. Tech and M. Tech degrees in 2011 in Microelectronics and VLSI at Indian Institute of Technology, Madras, India.

Indian Institute of Technology: BSIM-BULK

Dr. Yogesh Singh Chauhan

Dr Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with the Semiconductor Research & Development Center at IBM Bangalore from 2007- 2010; Tokyo Institute of Technology, Tokyo in 2010; University of California Berkeley from 2010-2012; and ST Microelectronics from 2003-2004. He is the developer of industry standard BSIM-BULK (formerly BSIM6) model for bulk MOSFETs and ASM-HEMT model for GaN HEMTs. His group is also involved in developing compact models for FinFET, Gate-All-Around FET, and FDSOI transistors and Negative Capacitance FETs.

School of Engineering at the Macquarie University, Sydney, Australia, ASM-HEMT

Dr. Sourabh Khandelwal

Dr. Sourabh Khandelwal is a faculty member in the School of Engineering at the Macquarie University, Sydney, Australia. He is the lead developer of the ASM-HEMT compact model, which is a new industry standard for GaN RF and power devices. He has been a research faculty at the University of South Florida. Prior to that, he was Manager of the Berkeley Device Modeling Center and a Postdoctoral Researcher at the BSIM group at the University of California Berkeley. He has published three books, and over 100 research articles in the area of semiconductor device modeling and circuit simulations.

University of Waterloo, MVSG_CMC

Dr. Lan Wei

Prof. Lan Wei received her B. S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M. S. and Ph. D. in Electrical Engineering from Stanford University, Stanford, USA in 2007 and 2010, respectively. She is currently an Assistant Professor at the University of Waterloo, Waterloo, Canada. Before her current position, she worked as a Member of Technical Staff at Altera Corporation (now part of Intel Corporation) in California, and as a Post-doctoral Associate at Microsystems Technology Laboratories in Massachusetts Institute of Technology. She has intensive experience in device physics-based compact modeling, including developing compact models for carbon-nanotube transistors and the MIT virtual-source transistor compact model for silicon MOSFET and GaN HEMT. Her other research interests include device-circuit interactive design and optimization, integrated nanoelectronic systems with low-dimensional materials, cryogenic CMOS device modeling and circuit design for quantum computing.

CMC Leadership

CMC Leadership represents the industry’s top semiconductor design companies and manufacturers.

In their role, they provide overall direction and guidance to the efforts of the members and the developers involved in CMC working groups.

Chair

Dr. Peter Lee

Micron Technology

Vice-Chair

Dr. Jushan Xie

Cadence Design Systems

Treasurer

Takeshi Naito

Kioxia Corp.

Secretary

Tanvir Morshed

GlobalFoundries