DAC is back and Si2 is celebrating with events highlighting standard interoperability solutions for silicon-to-systems
Si2 Low-Power Forum
Power and Energy Efficiency in the Age of AI
Co-Sponsored by IEEE CEDA
Leading design architects, academics, and EDA practitioners discuss trailblazing strategies for low-power and energy-efficient design, and how standards can help these efforts
Monday, July 11
11:30 AM – 3:30 PM Pacific
Room 215
San Francisco Marriott Marquis
AMA Conference Center
Webinar Available
Nagu Dhanwada
Senior Technical Staff Member
IBM
IEEE P2416 Working Group Chair
Introduction and Lunch
Si2 Unified Power Model and IEEE 2416 Update
Industry Perspectives
The future of designs, covering AI-infused, high-performance microprocessors and cutting-edge designs in mobile, embedded and IoT, and AI-specific accelerators
Pitfalls of Power Estimation for AI & Vision SoCs and How to Avoid Them
With the expansion of deep learning inference applications, performance requirements and resulting power dissipation vary significantly. As the power dissipation must fit within the power budget of the deep learning SoC and battery limitations of the target device, it is increasingly important to architect and design AI inference engines with power considerations in mind. This presentation will guide you through wide-ranging power reduction techniques to estimate and reduce power from the architecture phase through to IP/SoC sign-off.
You Will Learn
Fergus Casey
R&D Director
ARC Processor IP
Synopsys
About Fergus
Fergus Casey is Director of R&D for Processor IP at Synopsys, with responsibility for Processor IP development across a broad portfolio including ARC RISC/DSP Processors, Embedded Vision and AI engines, and Safety and Security ready cores. His team has been first to market with state-of-the-art AI, Security and Safety processors, and their products have won industry awards from the Linley Group and the Embedded Vision Alliance. Fergus holds a bachelor’s degree in electrical engineering from University College Cork, Ireland.
About Patrick
Patrick Groeneveld is a principal engineer at Cerebras Systems, a machine learning hardware startup that makes the world’s first monolithic supercomputer. Before that he worked for many years in the EDA industry. He was Chief Technologist at Magma Design Automation where he was part of the team that developed a groundbreaking RTL-to-GDS2 synthesis product. Patrick received his MSc and PhD degrees from Delft University of Technology in the Netherlands.
Patrick Groeneveld
Principal Engineer
Cerebras Systems
Machine Learning Hardware: From Milliwatt to Kilowatt
The extreme compute requirements of machine learning drives an entirely new generation of hardware. The compute-intensive ML training is generally done in data centers using re-purposed GPUs. This provides cost-efficient floating-point compute hardware that interfaces with the well-known TensorFlow ML platform. To run on a GPU, however, the training data and weights need to be segmented to fit the limited on-chip memory and bandwidth. Cerebras takes a radically different approach with a massive 22 x 22 cm monolithic chip that contains over 850,000 powerful compute cores with 2.4 trillion transistors. This massive wafer scale engine allows the entire ML model, including all weights, to remain stationary in hardware while only the training data is streamed in at very high speed. The flip side is a whopping 20kW power consumption.
You Will Learn
Systems Not Silicon: Low Power Confronts Machine Learning
Machine learning silicon is an industry passion, but too often fixates on hypothetical efficiency metrics and idealized workloads. A career’s worth of technical leadership experience suggests two key shifts in perspective:
- Think Systems: Consider the end-to-end application workloads not just the inference inner-loop for high-volume applications like real-time media intelligence
- Broaden Goals: Look at both execution and implementation efficiencies to make good engineering and product strategy choices.
You Will Learn
Chris Rowen
Vice President of Engineering
Cisco
About Chris
Chris Rowen is a Silicon Valley entrepreneur and technologist known for his groundbreaking work developing RISC microprocessors, domain-specific architectures and deep learning-based software. As Vice President of Engineering for Webex Collaboration AI, Chris leads an engineering and product team focused on building smarter, clearer and more seamless speech, audio, visual and relationship intelligence experiences. He is an IEEE Fellow, and holds greater than 40 U.S. and international patents, an MSEE and PhD in electrical engineering from Stanford and a BA in physics from Harvard.
Academic Perspectives
Design and power using AI analysis techniques such as neural networks, and the current challenges with power analysis tools, models, and flows
About Dr. Murmann
Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for machine learning.
Boris Murmann
Professor of Electrical Engineering
Stanford University
Breaking the Silos
The Need for a Holistic Design Methodology in Tiny ML Systems
As machine learning algorithms are marching closer to the physical sensors, the design of analog and digital subsystems is becoming more intertwined. In this context, this talk will articulate the need for a holistic design flow that considers cost functions across the system stack.
You Will Learn
Formalizing Design-space Exploration for Flexible AI Accelerators
The proliferation of AI across a variety of domains has led to the rise of domain-specific HW accelerators. This talk will discuss techniques to model the design-space of these AI accelerators–formally breaking the design-space into hardware resource assignment, dataflow, and tiling. We will also introduce techniques for sample-efficient design-space exploration for flexible AI accelerators.
You Will Learn
Tushar Krishna
Assistant Professor
School of Electrical and Computer Engineering
Georgia Tech University
About Dr. Krishna
Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He also serves as an Associate Director for the Center for Research into Novel Computing Hierarchies. He held the ON Semiconductor (Endowed) Junior Professorship from 2019-2021. Dr. Krishna has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). His research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems.
About Dr. Pedram
Massoud Pedram is the Charles Lee Powell professor of Electrical and Computer Engineering at the University of Southern California. His research interests include computer-aided design of VLSI circuits and systems, low-power electronics, energy storage systems, machine learning, quantum computing, and superconductive electronics. An IEEE fellow, Dr. Pedram has authored four books and more than 800 archival and conference papers.
Massoud Pedram
Professor of Electrical and Computer Engineering
University of Southern California
Low-Power Design of Neural Network Accelerators
Low–power design of custom neural network inference accelerators for battery-powered, wireless mobile and IoT devices is a key requirement. In this talk I will describe an approach for minimizing power consumption of such accelerators by replacing costly fixed-point multiply-and-accumulate operations with simple Boolean or multi-valued logic operations. Results on various types of vision networks will be presented to show the efficacy of this approach.
You Will Learn
Panel Discussion
Challenges in low-power design and standards, including IEEE Standard 2416-2019
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Jerry Frenkil, Technical Advisor, Si2 | IEEE 2416 Working Group Vice Chair
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Daniel Cross, Senior Principal Solutions Engineer, Cadence Design Systems | IEEE 1801 Working Group Member
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Kaladhar Radhakrishnan, Fellow, Intel
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Moderated by Leigh Anne Clevenger, Vice President, Technology, Si2