DAC is back and Si2 is celebrating with events highlighting standard interoperability solutions for silicon-to-systems
Design and power using AI analysis techniques such as neural networks, and the current challenges with power analysis tools, models, and flows
About Dr. Murmann
Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for machine learning.
Professor of Electrical Engineering
Breaking the Silos
The Need for a Holistic Design Methodology in Tiny ML Systems
As machine learning algorithms are marching closer to the physical sensors, the design of analog and digital subsystems is becoming more intertwined. In this context, this talk will articulate the need for a holistic design flow that considers cost functions across the system stack.
You Will Learn
State-of-the-art and challenges in tiny ML systems
Breakdown of energy consumers
Current techniques for low-energy design
Need for a more holistic design framework
Formalizing Design-space Exploration for Flexible AI Accelerators
The proliferation of AI across a variety of domains has led to the rise of domain-specific HW accelerators. This talk will discuss techniques to model the design-space of these AI accelerators–formally breaking the design-space into hardware resource assignment, dataflow, and tiling. We will also introduce techniques for sample-efficient design-space exploration for flexible AI accelerators.
You Will Learn
Data reuse in AI accelerators
Design-space and map-space
Modeling AI accelerators
Sample-efficient design-space exploration
School of Electrical and Computer Engineering
Georgia Tech University
About Dr. Krishna
Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He also serves as an Associate Director for the Center for Research into Novel Computing Hierarchies. He held the ON Semiconductor (Endowed) Junior Professorship from 2019-2021. Dr. Krishna has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). His research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems.
About Dr. Pedram
Massoud Pedram is the Charles Lee Powell professor of Electrical and Computer Engineering at the University of Southern California. His research interests include computer-aided design of VLSI circuits and systems, low-power electronics, energy storage systems, machine learning, quantum computing, and superconductive electronics. An IEEE fellow, Dr. Pedram has authored four books and more than 800 archival and conference papers.
Professor of Electrical and Computer Engineering
University of Southern California
Low-Power Design of Neural Network Accelerators
Low–power design of custom neural network inference accelerators for battery-powered, wireless mobile and IoT devices is a key requirement. In this talk I will describe an approach for minimizing power consumption of such accelerators by replacing costly fixed-point multiply-and-accumulate operations with simple Boolean or multi-valued logic operations. Results on various types of vision networks will be presented to show the efficacy of this approach.
You Will Learn
Architecture of neural network inference accelerators
Using logic synthesis to optimize the accelerator design
Challenges in low-power design and standards, including IEEE Standard 2416-2019
Jerry Frenkil, Technical Advisor, Si2 | IEEE 2416 Working Group Vice Chair
Daniel Cross, Senior Principal Solutions Engineer, Cadence Design Systems | IEEE1801 Working Group Member
Kaladhar Radhakrishnan, Fellow, Intel
Moderated by Leigh Anne Clevenger, Vice President, Technology, Si2