Industry and Academic members of Si2 SIGs and OWGs publish joint white papers and conference papers to summarize their position on a specific technical area to get consensus and wider feedback from the larger semiconductor community.
Authors
Natesan Venkateswaran, IBM
Chris Mueth, Keysight
Jon Haldorson, Qualcomm
Leigh Anne Clevenger, Si2
Data Management, Metadata, Traceability, EDA, Hub and Spoke
Abstract
We live in a data-driven world and the chip (including IP, ASIC, SoCs, and Systems) design, verification, manufacturing, and test teams are seeing an explosive growth in data. According to a recent survey conducted by Si2-TITAN, a typical engineer spends 3 hours every week on average in various aspects of data processing, leading to an estimated $750M in annual costs to the electronics industry. It is clear that data management is a huge challenge, and it is imperative that we identify solutions for navigating these hurdles in an efficient manner. In this whitepaper, we share the results from that survey and our recommendations for addressing some of the pressing data management challenges.
Authors
Kerim Kalafala, IBM
Hui Fu, Intel
W. Rhett Davis, North Carolina State University
Karthik Aadithya, Sandia National Laboratory
Leigh Anne Clevenger, Si2
Artificial Intelligence, Classification, EDA, Machine Learning
Abstract
Researchers at chip design companies, foundries, EDA tool suppliers, academic institutions, and national laboratories cannot investigate novel Machine Learning Algorithms without organized volumes of trusted, suitably labeled, non-proprietary design datafor training. Access to quality data is fundamental to advancements in machine learning. Undoubtedly, progress is being made in applying ML to EDA; however, big-payoff concepts require access to big data sets. The companies best positioned to make gains in this area are chipmakers with internal EDA and semiconductor development capabilities, with a reservoir of archived IC design and manufacturing data. Even then, processed data—data describing the human and tool actions that transpired at each process step,which are key to enable the next level of intelligent optimization—have often been left uncaptured, or, at least, uncaptured in a format usable to empower ML. A comprehensive solution to the data access and formatting challenges that collectively supports competitive, university, and company research and development, is sorely needed. This work presents motivation, requirements, and essential components for a collaborative, secure learning API for EDA, based on recent work by the Silicon Integration Initiative AI/ML in EDA Special Interest Group. Stakeholder authors,including chip design companies, foundries, academic institutions, and national laboratories, present their problem statements for a collaborative secure learning API through use case scenarios specifically targeting the ML training data gap.
Authors
Kerim Kalafala, IBM
Veeravanallur Parthasarathy, AMD
Norman Chang, ANSYS
Akhilesh Kumar, ANSYS
Elias Fallon, Cadence Design Systems
Sriram Madhavan, GLOBALFOUNDRIES
Prateek Bhansali, Intel Corporation
Srinivas Bodapati, Intel Corporation
Chandramouli Kashyap, Intel Corporation
James Masters, Intel Corporation
Ramy Iskander, Intento Design
Larg Weiland, PDF Solutions
Karthik Aadithya, Sandia National Laboratory
Boon-Siang Cheah, Synopsys
Mengdi He, Synopsys
Leigh Anne Clevenger, Si2
Artificial Intelligence, Classification, EDA, Machine Learning, Standards
This work explores industry perspectives on:
Abstract
A standard, common method for classification and structure of machine learning training and inference data for interoperability is critical to enable and accelerate the use of artificial intelligence and machine learning in semiconductor electronic design automation. Subject matter experts from across the semiconductor and EDA industry highlight the differences and common threads in developing industry standards for AI/ML in EDA application data for design areas including digital, analog, shapes-based and IP development. The authors conclude that in order to accelerate AI/ML applications for EDA, a collaborative and coordinated approach is needed. A prerequisite for this approach is establishing the best process for organizing, leveraging and sharing data. Si2 industry survey results show a gap in the availability and organization for AI/ML data in EDA. A common data model would address the data organization gap for chip developers, EDA tool developers, IP providers and researchers by first supporting the high interest EDA areas, design data and derived data.
Authors
Joydip Das, Samsung Austin R&D Center (SARC)
Akhilesh Kumar, Ansys
Aparna Dey, Cadence Design Systems
Sashi Obilisetty, Google LLC
Prateek Bhansali, Intel Corporation
Srinivas Bodapati, Intel Corporation
Hui Fu, Intel Corporation
Anoop Saha, Mentor, a Siemens Business
Rhett Davis, NC State University
Ryan Carey, Qualcomm
Rajeev Jain, Qualcomm
Karthik V. Aadithya, Sandia National Laboratory
Leigh Anne Clevenger, Si2
Artificial Intelligence, EDA, Electronic Design Automation, Machine Learning, Semiconductor
This paper evaluates the results of an industry-wide survey, covering:
Abstract
Semiconductor industry awareness of AI/ML in EDA has progressed such that results from a user survey can drive industry-wide standards and improvements. Silicon Integration Initiative conducted such a survey in April 2020 identifying gaps, opportunities, and current practice for incorporation of AI/ML into the EDA domain. This paper presents and analyzes the findings of the survey. Areas explored include the current state of ML adoption in EDA at the respondents’ organizations and areas for potential improvement where respondents felt a certain level of dissatisfaction with the current state of ML availability and adoption within their organizations as well as their fields. Each respondent identified his or her areas of interest related to EDA. The goal of this analysis is to understand the challenges to adoption and potential improvements to AI and ML techniques in EDA. This will benefit EDA tool vendors and end-user engineers as well as individuals from academia, industrial design houses, and national laboratories. Future work by research and development groups can support these efforts through the development of a common AI/ML in EDA ecosystem.
