Silicon Integration Initiative Inc. (Si2), a research and development joint venture providing standard interoperability solutions for IC design tools, has launched a working group to standardize a new, formal declarative language that greatly simplifies finding and correcting design flaws in complex, leading-edge chip designs early in a design flow. Named OPAL (Open Pattern Analysis for Layout), […]
Tom Whipple, solutions architect at Zuken, has been reelected chair of the Si2 Chip-Package Co-Design Technical Advisory Board. The TAB’s primary goal is to identify problems in chip-package-board design flows, and flows and data exchange solutions to solve them.
At Zuken, Tom is responsible for defining, promoting and supporting chip-package-board co-design solutions using Zuken CR-8000 design tools.
Si2 Contributes Advanced IC Power
Modeling Technology to IEEE
Technology will improve SoC design for power efficiency
AUSTIN, Texas–Silicon Integration Initiative, Inc. (Si2), a leading integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.
Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”
IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent. Its latest update, IEEE 1801-2015, includes support for power-state modeling. “P2416 provides power data representations to complement 1801 power-state modeling. Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction” Frenkil added.
Organizations that contributed to the model development are: ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.
Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”
“This new modeling technology is the first significant advance in power modeling in quite a long time” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort. “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”
Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip. Si2’s contribution is a major step toward addressing that need.”
The IEEE-P2416 Working Group has already started reviewing the Si2 contribution. In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.
This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.
For more information about this project, contact Jerry Frenkil at Jfrenkil@si2.org. For information about the Si2 Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.
Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.
Si2 announces the second in a series of member-only webinars focusing on XML–Introduction to XML Schemas.
XML schemas are the normative definitions of any XML-based standard. The schema defines the domain- specific vocabulary (DSV) and types of values in an XML database. The XML database must conform to its schemas, using the predefined elements and entering values that are compliant with the schema.
10:00 a.m.-11:00 a.m. PST
For more information click here.
Many Si2 OpenStandards are based on XML, the eXtensible Markup Language. XML files have a consistent syntax and, combined with the domain specific vocabulary defined in the Open Process Specification (OPS) schemas, succinctly capture the data used to model the IC fabrication process to the design tools.
The OPS XML database contains the constraints, layers, stacks, devices and rules that represent the fabrication process in a vendor-neutral format. This single source for the data is used to generate process design kits.
About the Course
This introductory course focuses on the XML file syntax that will help you create well-formed XML files. Through lecture, quizzes and labs, you will examine the syntax of XML elements and learn how to create, modify or read and understand an OPS XML file. We will explore the file format, elements and attributes, namespaces and connecting to schemas.
Prerequisites: A willingness to learn XML and an interest in OPS.
- Exploring XML
— XML editors
— What is XML and why do we use it?
— How do you use OPS XML?
— What is a valid XML file?
- XML File Format
— XML prologue and comments
— XML element declaration
— Sub-elements and content value
- Namespaces and Schemas
The example used in the class is a single OPS XML hierarchy that will be used for future courses in this series. A recording will be available on the Si2 Community web site.
Who Should Attend
Si2 member company employees who work with, create, edit or read XML data files are invited to attend this free webinar.
Si2 Interoperability Standards Architect
ADVANCED REGISTRATION REQUIRED
CLICK HERE TO REGISTER
Future Courses for Si2 Members
Si2 will offer additional XML classes Announcements will be made by email and on our web site, www.si2.org.
- OpenStandard Schemas
- XML editors
- XML utilities
- XML Python Parser
- Writing ASCII technology files from OPS XML
- Inputting comma separated value (CSV) files
- Xinclude – Building a process database
AUSTIN, Texas–Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, has launched a project to help designers reduce power consumption, a growing challenge for most system-on-chip designs. The project will develop new power modeling technology to estimate power consumption more easily and more accurately throughout the design process, especially during the earliest stages.
The end result will be a new power modeling standard to reduce resources and costs needed to develop virtually every type of SoC. Jerry Frenkil, director of OpenStandards, said that the Si2 Low Power Working Group, part of the newly restructured Si2 OpenStandards program, will lead this industry-wide effort.
“Every SoC design team is grappling with the continued need to reduce power consumption,” Frenkil said. “That’s especially true for mobile devices, but it’s also a concern throughout the electronics industry. One way to accomplish this is through improved multi-level power modeling techniques that better predict SoC power and performance. Right now there’s no commonly accepted way to develop an accurate estimation of power consumption early in the design phase. This often leads to designs being power inefficient, performance constrained, or both.”
Frenkil said the standard will also “enable more efficient and reliable power analyses and optimizations since the same model will be used from system-level design through gate level implementation and all phases in between.”
The approved specification will be contributed to the IEEE P2416 Standards Working Group for industry-wide distribution. Nagu Dhanwada, senior R&D engineer at IBM, chairs both the IEEE P2416 and Si2 Low Power Modeling Working Groups. “Since Si2 is an R&D joint venture, its members can work together to develop specifications, tests and proof-of-concepts with anti-trust protection. This specification will greatly accelerate standardization efforts within P2416, and testing prior to IEEE standardization will enable us to rapidly prove out the use of the new standard before it hits the street,” Dhanwada explained.
IEEE P2416 is an essential component of a coordinated IEEE effort focusing on system-level design. The IEEE 1801 standard currently expresses design intent. It’s latest update, IEEE 1801-2015, includes support for power modeling.
John Biggs, co-founder and consultant engineer at ARM, chairs the IEEE 1801 Working Group. “Efforts of the Si2 Low Power Working Group will help the IEEE P2416 Working Group standardize the representation of power consumption data,” Biggs said. The fruits of this work, in combination with the new power modeling capability in IEEE 1801-2015, should greatly ease the challenging task of energy-aware system level design.”
The new Si2 model specification is expected to be completed in October. For more information about this project, contact Jerry Frenkil at Jfrenkil@si2.org. For information about the Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.
Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.
Si2 is planning to launch its first special interest group, which will focus on process design kits. Ted Paone, interoperability standards architect, said the SIG will “refine the methodology to improve process data and create quality process design kits.” Special interest groups are open to all Si2 members. For more information contact Ted Paone, email@example.com
OpenStandards, Si2’s newest member initiative, is the product of extensive member research and the core of a streamlined standards development process.
John Ellis, president and CEO, said market research and industry trends identified factors key to the creation of OpenStandards. “Speed and agility topped the list. The ability to quickly identify and create a needed standard are paramount.
“OpenStandards combines independent coalitions, technical advisory boards and new working into one, single-fee membership. Costs are reduced since companies can choose to participate in every activity, at any level, for one fee,” Ellis explained. “More than 90 percent of our members saw their dues decrease in 2016.”
This was accomplished while maintaining the mandated safe-haven, anti-trust protection, he added. Activities currently part of OpenStandards are Chip-Package Codesign (3D), Design for Manufacturability, Low Power, OpenPDK, and Silicon Photonics.
Jerry Frenkil, director of OpenStandards, manages this program. Co-founder of Sente, he has more than 30 years’ experience in the semiconductor and EDA industries.
Si2 will explain the OpenStandards concept during a free webinar on Tuesday, January 26, 9-10 a.m. PST.
10:00 a.m.-11:00 a.m. PST
Process design kits model the process for the design tools. The design kit contains the models; the device parameters, symbols and pcells, verification and extraction decks, and support for the tools in the design flow. Since new processes are much more complex, a PDK is generated for each variant of a process. The PDK can be targeted to specific markets by including additional devices and process information. The result is that quality PDK creation is more important to the design success than ever before.
This panel will discuss the PDK generation methodology, from the capture of the process data, inputs to the PDK generation system and creation of the PDK for delivery, to the design groups. We will investigate the challenges and look for proposed solutions which can be implemented collaboratively.
Moderator: Ted Paone, Interoperability Standards Architect, Si2
Joerg Doblaski, Director of Design Support, X-FAB Group
Sue Strang, Senior Engineer, Research Division, IBM
Dan Clein, Technical Director, Sankalp Semiconductor
Dr. David Onsongo, Qualcomm
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