IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard

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Si2 has announced  that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly in to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

Simplified Power Modeling

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models.  P2416 is scheduled for balloting in early 2019.

Industry Contributions

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods.  “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM.  “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard.  Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

Ready for P2416 Balloting

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project.  “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization.  We anticipate going to ballot early next year.”

For more information about this project, contact Jerry Frenkil at [email protected].  For information about the Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.

New Si2 Working Group to Develop Unified Power Model for System-Level IC Design

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AUSTIN—Silicon Integration Initiative, Inc. (Si2), a research and development joint venture focused on integrated circuit design tool interoperability standards, has launched a System Level Power working group to create the Si2 Unified Power Model (UPM), a standard which will strengthen power management in system-level IC design.

Jerry Frenkil, director of the OpenStandards Coalition, which incubates new Si2 standards, said development of the Si2 UPM is part of the industry’s ongoing effort to improve energy and power efficiency throughout the system-on-a-chip development flow, with a focus on system design.

“Energy efficiency is a growing and costly constraint in integrated circuit design,” Frenkil explained.  “There’s currently no standard, single model to represent power data at the system level across a range of process, voltage, and temperature (PVT) points.  Different, often inconsistent models are currently used in each of the three major stages of IC design:  system design, register transfer level (RTL) design, and implementation.  None of those models currently support voltage or temperature dependencies.  The Si2 UPM addresses those issues.”

When completed, the Si2 UPM will enable faster turnaround time for system-level power and thermal analyses, as well as reduce resources and costs incurred in power model generation, Frenkil said.  The approved specification, including the capability to supply power data to IEEE 1801/UPF power state models, will be contributed to the IEEE P2416 Working Group for ongoing maintenance and industry-wide standardization. IEEE P2416 supports the ability to develop accurate, efficient and interoperable power models for complex, integrated circuit designs.

Si2 members participating in the working group are ANSYS (NASDAQ: ANNS), Cadence Design Systems (NASDAQ: CDNS), IBM (NYSE: IBM), Intel (NASDAQ: INTC) and Entasys.

The Si2 UPM will benefit the three major constituencies to the IC design ecosystem:

  • For IP providers:
    • A system-level power data model companion for the IEEE 1801 (UPF) power state model
    • reduced time and resources for model and library generation and support.
  • For system and SoC architects
    • true system-level modeling that eliminates the need for gate-level netlists.
    • faster turn-around time for system-level power and thermal analyses
    • model consistency across abstractions
  • For EDA providers
    • New, non-cannibalistic product and solution opportunities

For information about the new Si2 UPM working group or other Si2 OpenStandards projects, contact Jerry Frenkil, jfrenkil@si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Si2 contributes advanced IC power modeling technology to IEEE.

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Si2 Contributes Advanced IC Power
Modeling Technology to IEEE

Technology will improve SoC design for power efficiency

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AUSTIN, Texas–Silicon Integration Initiative, Inc. (Si2), a leading integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.

Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”

IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent.  Its latest update, IEEE 1801-2015, includes support for power-state modeling.  “P2416 provides power data representations to complement 1801 power-state modeling.  Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction” Frenkil added.

Organizations that contributed to the model development are:  ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.

Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”

“This new modeling technology is the first significant advance in power modeling in quite a long time” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort.  “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”

Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip.  Si2’s contribution is a major step toward addressing that need.”

The IEEE-P2416 Working Group has already started reviewing the Si2 contribution.  In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.

This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.

For more information about this project, contact Jerry Frenkil at [email protected].  For information about the Si2 Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

Si2 Low Power Membership Agreement

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The Si2 LOW POWER COALITION  requires the following membership agreements:

First:  LOW POWER COALITION MEMBERSHIP AGREEMENT 01/2008

Second:  Low Power Coalition Operating Rules