All System-on-chip (SoC) designs today face low power design issues of one sort or another–maximizing battery life, sizing power grids, controlling leakage power, verifying power sequencing, estimating and modeling power at various abstractions, analyzing electro-thermal effects and utilizing power intent standards. The list goes on and on. This panel explores current methods for dealing with the many critical power issues along with limitations of those methods. Both design and the design automation perspectives are offered.

What you will learn

  • Best practices from low power design leaders
  • New developments in power modeling
  • Challenges and solutions for power aware system-level design


  • Moderator: Jerry Frenkil, Director of OpenStandards, Si2
  • Nagu Dhanwada, Low Power Tools and Methodology Lead, IBM
  • Aaron Grenat, Fellow Design Engineer, AMD
  • John Redmond, Associate Technical Director for Digital Video, Broadcom
  • Frank Schirrmeister, Senior Group Director, Product Management & Marketing, Cadence Design Systems