Si2’s value to our member companies is a result of the collective leadership and collaborative efforts of Si2 staff and leaders from member companies and academia. This has never been more evident than in the last quarter where there has been considerable progress made on improving OpenAccess, releasing new Compact SPICE models and defining the next steps for enabling 3D-IC, AI/ML for EDA, and standard IP and system level power models. In this update I will touch on some of these activities. If your company is not yet a member of Si2 and you want to learn more, please contact me********@si*.org . If your company already is a member of Si2 (or you are unsure) and you want to get involved, please contact the people noted in each section.
Before I begin though, I want to congratulate four new members of our Board of Directors who joined since I last gave an update:
- Hong Sok Choi,Vice President Computer Aided Engineering Group, SK-Hynix
- Niels Faché, Vice President and General Manager, Keysight EDA
- Lluis Paris, Senior Director, 3DFabric Alliance, TSMC
- Juan C. Rey, Vice President of Government Programs, Siemens EDA
Congratulations to the 2024 POP Award Recipients
I also want to congratulate the two winners of Si2’s annual Power of Partnership Award. The first award was a special corporate award that went to the Cadence Design OpenAccess Implementation Team which is responsible for developing the Si2 OpenAccess API. This group is the dynamic development arm of Cadence Design Systems’ OpenAccess integration effort. The team collaborates closely with the Si2 OpenAccess Change Team and other corporate members of the Si2 OpenAccess Coalition. They are responsible for the enhancements and new capabilities that ensure the OpenAccess API remains at the cutting edge of the EDA industry’s changes.
The second POP award went to the Open Model Interface Working Group that drives the development of OMI, an Si2 standard, C-language application programming interface that supports SPICE compact model extensions. In 2024, the OMI working group released a groundbreaking new version to support non-MOSFET devices. That release paves the way for heterogeneously integrated technologies on the cutting edge of semiconductor design. The working group transcended its initial limitations to encompass a more diverse set of devices, including bipolar models. This release of OMI holds universal applicability across all models, unlocking numerous possibilities for device evaluation and reliability.
OpenAccess Usability Takes Another Step Forward
The OA Coalition has been busy on several fronts, but I want to highlight one activity in particular that relates to our efforts to improve usability. As many OA users know, building OpenAccess is a complex task when it must be done from source code. There are considerable dependencies necessary for a successful build such as version compatibility, compiler option settings, and several required utilities. The result is a matrix of dependencies that are difficult to communicate. To overcome this, a new oaBuilder has been built to clearly communicate dependencies to the user. The oaBuilder checks the environment configuration, version compatibility, identifies missing utilities and dependent software and validates the environment before launching a long compile process. oaBuilder in now in Beta testing and will be available by the end of 2024. To learn more about OpenAccess please contact ma************@si*.org.
Planning Kicked-Off for the 2025 Inaugural Compact Model Conference
The Compact Model Coalition (CMC) made two (2) production releases and seven (7) Beta releases in last quarter. MVSG v 4.0.0 was released on April 16th 2024 and L_UTSOI v. 102.8.0 was released on May 31st 2024. In an exciting move, the CMC officers approved the creation of the inaugural International Compact Model Conference (ICMC) targeting the summer ‘25. Current plans are for it to occur in the same week as the Design Automation Conference (DAC 25) and the quarterly CMC member meeting. Stay tuned for more information on this soon. To learn more about the CMC please contact le*****************@si*.org.
Fast and Accurate IP and System Level Power Analysis is On the Horizon
Today, SoC designers analyze leakage and dynamic power over a range of abstraction levels as they integrate standard cell libraries and IP blocks from internal and 3rd party sources. Currently there is no industry standard specification in use for power model data calculation, so companies develop data translations between proprietary models and combine power results using spreadsheets and custom programs. These are complex and time-consuming to scale for the large number of PVT corners that one may want to evaluate. As the industry moves to ever more levels of abstraction with 3D-ICs and new sources of IPs and chiplets this problem will continue to grow.
Si2’s Unified Power and Thermal Coalition (UPTC) is addressing this challenge by enabling the adoption of the IEEE 2416 and UPM 2.1 standards for leakage and dynamic power modeling that come with formally documented schemas. The UPTC is co-developing a UPM software suite that UPTC member companies can use for end-to-end PoC’s that span standard cell libraries to the IP block and system level. UPTC members include Qualcomm (chair), IBM (chair), Samsung, Intel, NXP, and Cadence.
Currently, there are two major POCs underway. The UPM software suite is running at Qualcomm. Qualcomm is using IEEE 2416 at the IP block level to develop equations and use the UPM “scenario” files to analyze leakage and dynamic power. The equations are currently generated by their own solutions that incorporate any parameter of interest (temp, voltage etc.). Also, in 2023-24, Samsung started implementing IEEE 2416/UPM leakage analysis for an opensource AES128 circuit using the Nangate15 lib. Samsung has installed the UPM software suite and is now running it on-site. Samsung is now extracting and characterizing contributors for UPM models for their proprietary std cell library for the AES128.
In parallel, a UPM working group is focusing on demonstrating new features of UPM 2.1 and IEEE 2416 to improve the specification. In 2023-24 they focused on applying UPM 2.1 to a mixed-signal radio SoC and demonstrated the results at DAC in a poster session. The UPTC is poised for a major step forward in the next year as Si2 increases its engineering investment to implement a complete reference implementation for the IP and system level in 2025. To learn more about the UPTC please contact le*****************@si*.org.
A Path to Enable Efficient Academia-Industry Collaboration on AI/ML for EDA
A lack of standardized representation in support of AI/ML algorithms and data analytics makes it hard for academia to compare AI/ML results and makes the sharing of the algorithms themselves very difficult. EDA vendors have enhanced their offerings by embedding AI/ML capabilities and an effort is needed to supplement those efforts with an open system that can be shared between universities and industry. A standardized schema will help promote industry/academic collaboration and will enable sharing of AI/ML algorithm efforts without requiring companies to share their data. This will result in:
- Improved industry/academic collaboration (Academic efforts can be more easily compared)
- Better IP protection: Companies can use the schema to try algorithms without exposing their data.
- Improved efficiency: A common implementation means entities don’t have to develop their own.
- More Reuse: ML training and inference can be reused across orgs without exposing data outside.
With this in mind, a new OpenStandards working group (OWG) was just approved by the Si2 Board of Directors to focus on providing a standardized schema specification which provides good support for AI/ML algorithms and data analytics. The OWG will specify requirements and priorities and feed those into two existing academic schema projects, EDA Schema from Drexel University, and CircuitOps from ASU and Nvidia.
The members of the Special Interest Group that proposed the formation of the OpenStandards Working Group (OWG) are AMD, Ansys, IBM, Intel, NXP, Qualcomm, Siemens, Silvaco, Drexel University, and Arizona State University (ASU). The output of this OWG will be documented schema specifications and schema implementation from the two university partners. We are currently soliciting members for the OWG, starting with the members of the AI/ML for EDA SIG. To learn more about this new OpenStandards working group please contact le*****************@si*.org.
Starting to Tame the Wild West of 3D-IC
3D-ICs have gained a lot of attention due to their technological promise and complexity. TSMC and Samsung have formed industry-wide alliances that bring together IC and package EDA suppliers, design companies, OSATs, and others to converge on the means to more easily bridge those worlds. The new National Advanced Packaging and Manufacturing Program (NAPMP) funded by Chips for America has an R&D focus area on enabling the Chiplet eco-system. Before that, the US Dept. of Defense initiated the State-of-the-Art Heterogeneous Integrated Packaging (SHIP) program led by Intel and Qorvo with BAE Systems. In parallel, the Open Compute Program (OCP) initiative around the “Open Chiplet Economy” plans to create a core set of adaptable standards and tools that facilitate chiplet-based product design and manufacturing. Despite these efforts, or maybe because of the number of overlapping efforts, a common set of standards that will enable seamless design and integration across a 3D-IC remains elusive.
One example is Assembly Design Rules (ADR) that are needed early in the 3D-IC planning process that specify the constraints that must be met to satisfy design rules set by 3D-IC package and assembly providers. The rules include spacing rules about the bumps on chip interfaces, spacing rules between chip edges, size rules for chips, and stacking rules for chips. Chip designers need to follow these rules to ensure that chips can be assembled properly into 3D-IC packages. System designers using 3D packages need to follow these rules to ensure that they do not violate assembly rules provided by their package vendors.
Because 3D-IC systems may include chips and assembly steps provided by multiple vendors there is a need for a standard format to enable needed interoperability. As noted, there are existing efforts to standardize in areas like this. Si2 does not need to define and champion a new standard. Si2’s value is in the ability to co-develop POC demonstrations, compliance suites, utilities, reference implementations, and other sharable IP in addition to and in support of an existing standard specification for the benefit of our members. As a neutral third party, Si2 is a natural place to drive conversations to converge onto one standard and then provide the common technology and IP needed to enable the standard while also enabling interoperability with other approaches while the industry converges.
Most of the major players in this space are members of the Si2 Board of Directors. In the last six months there has been a lot of discussion on this topic with a consensus starting to form on the role Si2 should play. Stay tuned for more updates on this topic in the next Si2 update. Meanwhile, if you want more information or want to get involved, please contact le*****************@si*.org.
