Welcome to my Q2 2025 update. In this update I welcome Banghyun Sung from SK hynix to the Si2 Board of Directors, invite everyone to check out the International Compact Modeling Conference (ICMC 2025), give a quick update on the AI/ML in EDA SIG and AI/ML Schema OpenStandards Working Group, and invite you to join us at several complimentary Si2 DAC events on 6/22 and 6/24 (Si2 Events at DAC).
If you are interested in learning more about any of the topics or Si2, please contact us at Contact Si2.
Banghyun Sung (SK hynix) Joins the Si2 Board of Directors
First, I would like to welcome Banghyun Sung of SK hynix to the Si2 Board of Directors. Banghyun is a Distinguished Engineer in SK Hynix where he is responsible for various technical tasks to further develop the design automation environment for SK hynix’s HBM, DRAM, NAND and CIS products. He majored in VLSI/CAD and joined SK hynix in 2007 as a Computer Aided Engineering group. He mainly developed in-house tools for verification of full-custom designs such as Static/Dynamic ERC, Cross-talk analysis, and Aging simulation tools. He also developed various design automation environments such as Design modeling, Design Optimization, and PKG analysis. Before that, he was in charge of Circuit simulators including FineSim and IR-drop simulation environments in SK hynix. In order to introduce the Open-Access API to SK hynix, he promoted the Si2 membership in 2011 and developed various design automation tools using the Open-Access API. In addition, since 2020, he has been working as the SK hynix representative for the Open-Access Coalition and is in charge of disseminating information on various W/Gs under Si2 within SK Hynix.
Join us at the International Compact Modeling Conference
June 26, 27 2025 at the Clift Sonesta Hotel, San Francisco
The innovative inaugural International Compact Modeling Conference (ICMC 2025) brings academia and industry partners together to share advances in the development, broad application, and standardization of compact models for semiconductor devices. The conference is co-sponsored by the IEEE, Si2, the IEEE Electron Devices Society, and the IEEE Microwave Theory & Techniques Society (MTTS). Corporate Sponsors are Micron, Qualcomm, Sandia National Labs, Siemens, and Silvaco. The conference will be held at the Clift Sonesta hotel in San Francisco just after DAC on June 26-27. For more information on the program and registration please click on the link above.
Advances in AI/ML at Si2
The AI/ML in EDA SIG
The Si2 AI/ML in EDA SIG is continuing in our 6th year to discuss and debate best practices to optimize semiconductor design flows, focusing on industry gaps in models and knowledge. Notable so far in 2025:
- Members of the SIG are planning to participate in the 2nd International Conference on LLM-Aided Design (ICLAD, https://iclad.ai/), proposing a panel discussion on creating industry-wide foundational models for EDA/SoC design. Marc Rose, Si2, is coordinating this with proposed topics including foundational model validation, criteria, evaluation, and industry acceptance.
- Ziyu Deng, graduate student at NC State, presented on work inspired by the Si2 AI/ML Speed API OWG discussions in 2023/2024: How companies can share data with research institutions for model development while limiting the ability of other companies to infer or gain access to the data. The work explored methods such as data obfuscation, differential privacy, and transfer learning to balance model quality with privacy concerns.
- Leigh Anne Clevenger, Si2, presented an overview of the Center for Advanced Electronics through Machine Learning (CAEML, https://caeml.illinois.edu/) publications and webinars which are publicly available, and described topics including running LLMs on limited hardware and 3DIC parameter optimization. Leigh Anne is chair of the CAEML Industry Advisory Board.
- Active industry and academic members include Ansys, IBM, Intel, Qualcomm, NXP, Samsung, Siemens EDA, Silvaco, Synopsys, Arizona State University, Drexel University, NCSU, UC San Diego
The AI/ML Schema OpenStandards Working Group: Knowledge representation for EDA
The AI/ML Schema OWG, led by chair Ivan Kissiov (Siemens), and working with researchers from Drexel University and Arizona State University, is providing a unified framework for preparing circuit design data and meta-data to feed machine learning algorithms. Members are working with the OpenAccess team on a path from OA to this framework. The work builds on current university research using state-of-the-art software and methods and will be available first to Si2 OpenStandards Working Group industry and academic members. As described by Kissiov, the elements and their role in the integrated framework are:
- The schema validates input data
- The taxonomy organizes components
- The ontology defines relationships
- The knowledge Graph tracks dependencies
- The label Property Graph adds context
The practical benefits include:
- Standardized data exchange
- Automated verification
- Knowledge preservation
- Impact analysis
- Design optimization
Si2 at DAC
Si2 will be hosting several events at DAC this year on Sunday June 22 and Tuesday June 24. The events are described below. Some are open to the public while others are only open to employees from Si2 member companies. For more information and to register please visit this Link
I want to highlight the annual Si2 Member Celebration that will take place on Tuesday from 4:00-6:00pm in Moscone West Room 3016. We will be giving a quick recap of the last year, handing out our annual Power of Partnership award, and listening to a talk on “Evaluation of LLMs for Si Design” by Nathaniel Pinckney, Sr. Research Scientist at Nvidia. This will be followed by a reception where we can network and enjoy some good food and beverages. Details of each event are below. Look for more information in your inbox between now and the beginning of DAC.
Tutorial: Powering the Future: Mastering IEEE 2416 System-Level Power Modeling Standard for Low-Power AI and Beyond
Sunday, June 22, 9:00 – 12:30 PM, Moscone West, Room 3008 Register at www.dac.com
This tutorial will provide attendees with a comprehensive understanding of the IEEE 2416 standard, used for system-level power modeling in the design and analysis of integrated circuits and systems. Participants will gain practical knowledge necessary to implement and utilize the standard effectively. The tutorial will highlight the pressing need for low-power design methodologies, particularly in cutting-edge fields like AI, where computational demands are high. By getting a clear understanding of the IEEE 2416 standard, attendees will be equipped to make decisions on how the standard can be incorporated into their design flow to deliver the efficiencies needed to build their cutting edge low power designs. The presenters, who are experts from different industry segments (EDA, Foundry, SoC and IP) and academia who will use the IEEE 2416 standard positioned for a 2025 release.
Agenda
- Introduction to IEEE 2416 and Power Modeling Evolution
- Core Concepts of IEEE 2416 – Digital and AMS Highlights
- Real-World Applications – Industry Deep Dives
- System-Level Example: AI Accelerator with AMS Blocks
Who Should Attend
- IP Developers: Engineers responsible for designing and characterizing IP blocks who need to create accurate and efficient power models.
- SoC Architects and Designers: Professionals involved in system-level design and integration who require a deep understanding of power analysis and optimization using the 2416 standard.
- EDA Tool Providers and Users: Developers and users of EDA tools who integrate and leverage the capabilities of the 2416 standard in their workflows.
Authors
- Daniel Cross, Cadence Design Systems
- Rhett Davis, NCSU
- Eunju Hwang, Samsung
- Tavares Forby, Qualcomm
- Akil Sutton, IBM
Organizers
- Nagu Dhanwada, IBM
- Leigh Anne Clevenger, Si2
IEEE 2416 System Power Modeling Working Group Open Meeting
Tuesday, June 24, 10:00 – 11:30 AM, Moscone West, Room 3016
REGISTRATION REQUIRED, Register Here
In the current dynamically changing landscape of computing, the growth of artificial intelligence (AI) applications has caused an exponential increase in energy consumption, re-emphasizing the need for managing power footprint in chip design.
To manage this escalating energy footprint and enable true system-level low-power design, modeling standards play a key role in facilitating interoperability and re-use. The IEEE 2416 system-level power modeling standard, introduced in 2019, offers a unified framework spanning system-level to detailed design, facilitating comprehensive low power design for entire systems. This standard enables efficiency through contributor-based process, voltage, and temperature (PVT) independent power modeling.
The IEEE 2416 standard is currently positioned for a 2025 release with production industry-driven extensions in analog/mixed-signal, system modeling, and multi-voltage scenarios. Join this open meeting of the IEEE 2416 committee to learn how this new release will enhance system power modeling productivity for you and your company.
Discussions Include
- New features in IEEE 2416-2025
- Ballot pool feedback and associated actions
- Standardization schedule
Organizer: Nagu Dhanwada, Chair of IEEE 2416, IBM
Panel — Powering the Future of AI: Are Standards an Enabler or a Bottleneck?
Tuesday, June 24, 12:00 – 1:00 PM, Moscone West, Room 3016
Free Lunch for the First 50 Attendees
REGISTRATION REQUIRED, Register Here
As AI workloads scale dramatically, power, thermal management, and reliability have emerged as critical concerns. Industry standards such as IEEE 2416 and IEEE 1801 have attempted to address these issues through system-level power and thermal modeling. But are these standards accelerating innovation, or have they become a bottleneck for rapid technological advancement?
Powering the Future of AI features panelists from industry leaders in design and methodology for power and thermal optimization, including IBM and Cadence Design Systems. The lunch forum includes experienced leaders in the semiconductor industry and EDA standardization and targets system designers and architects, logic and circuit designers, validation engineers, CAD managers, researchers, and academicians
Key Discussion Points
- Standards: Foundation or Constraint to Innovation in AI and system-level power management?
- Practical impacts and industry adoption: Real-world experiences from semiconductor foundries, AI hardware developers, and system integrators.
- Bridging Gaps: The role of emerging IEEE 2416 extensions (A/MS, thermal, multi-voltage) in addressing AI workloads.
- Cross-industry perspectives from EDA tool vendors, system integrators, and IP developers.
- How should standards evolve to effectively enable next-generation AI applications?
Panelists
- Nagu Dhanwada, IBM, Moderator
- Sri Chilukuri, Arm
- Amit Srivastava, Synopsys
- Karan Sahni, Cadence Design Systems
- Rhett Davis, NCSU
Si2 OpenAccess Coalition Forum
Tuesday, June 24, 1:00 – 2:45 PM, Moscone West, Room 3016
Free Lunch for the First 50 Attendees
REGISTRATION REQUIRED, Register Here
The OpenAccess Coalition Forum features innovations from industry experts, with topics ranging from curvilinear and 3D design to multi-threading performance improvements enabled by the OpenAccess API. Presenters from coalition member companies representing successful start-ups, international design companies, and academia, will discuss the strengths of OpenAccess technology and the value of membership.
Who Should Attend
- System designers and architects
- Logic and circuit designers
- Validation engineers
- CAD managers
- Researchers and academicians
Presentations
- Curvilinear Design and Application – Aki Fujimura, CEO Design 2 Silicon
- How to Improve Performance and Connect with EDA Software Using the Open-Access API – Yong-Hwan Jeon (Jason), CAD Engineer SK-hynix
- An AI-Powered IC Routing – Ed Grenert, Founder Frontier Design Automation
- Fast Connectivity Highlighting with Polygon Operators Extension – Simone Comensoli, Staff Software Systems Engineer PDF Solutions
- Heterogeneous 3D Design with OpenAccess – Rhett Davis, Professor Electrical and Computer Engineering NCSU
Si2 Annual Member Meeting and Power of Partnerships Award Celebration
Tuesday, June 24, 4:00 – 6:00 PM, Moscone West, Room 3016
For Si2 members and their guests
REGISTRATION REQUIRED, Register Here
Join us for a celebration of collaboration at our annual members’ meeting and reception. Gather with members, the board of directors, staff, and special guests as we toast to our joint achievements over the past year and see a sneak preview of our newest initiatives.
Agenda
- Welcome and Si2 year in review
- Annual Power of Partnership Award
- Evaluation of LLMs for Si Design – Nathaniel Pinckney, Sr. Research Scientist, Nvidia
- Networking Reception (Hors D’oerves, beer and wine)
Don’t miss this opportunity to celebrate, network and ignite new ideas. Admission is complimentary for Si2 members and their guests.
