By Robert Aslett
President and CEO
Silicon Integration Initiative
If you are interested in learning more about Si2, please contact us at Contact Si2.
Welcome Wilbur Luo to the Si2 Board of Directors
I want to start off by welcoming a new member to the Si2 Board of Directors. Wilbur Luo will join the Si2 Board to replace Michael Jackson who represented Cadence on the Si2 Board since 2022. Wilbur is Vice President of Product Engineering for Custom IC at Cadence. His team of engineers is responsible for product and solution definition, expert-level customer support and engagement, and tool enablement with foundries, partners and customers for the entire custom IC, analog and RF tool chain. Before this role, he was responsible for product management, product marketing and business development teams for the Custom IC and PCB division. He also managed the Design for Manufacturing (DFM) R&D group and launched the next-generation custom/mixed-signal, high-performance routing and yield optimization solutions at Cadence. Wilbur lives in Southern California and joined Cadence in 2002. He has worked in the semiconductor and EDA industry for over 30 years. Since graduating from UC Berkeley in Electrical Engineering and Computer Science, he has worked on technologies spanning the entire design flow at Forte Design Systems, Cypress Semiconductor and AMD. Welcome aboard, Wilbur!
Welcome the Si2 OpenAccess Coalition Officers for 2025
I want to also welcome back the five semiconductor industry technologists who have been reelected as officers of the Si2 Open Access Coalition. The officers oversee the development of OpenAccess and play a crucial role in setting the strategic direction, making key decisions, and ensuring the smooth operation of the coalition. As part of the earlier announcement regarding this, Marshall Tiner, senior director of OpenAccess, said, “The OA coalition constantly synchronizes the API and database with electronic design automation tools This relentless collaboration with the top EDA suppliers, IP providers, design companies, and the integrator company provides an open standard API that enables different tools from various vendors to seamlessly interact with each other.” The OAC officers for 2025 are:
- Chair: Ramond Rodriguez, Sr. Director of Advanced CAD Capabilities at Intel
- Vice Chair: Hongmei Li, Engineering Manager at IBM
- Change Team Architect: Mark Rossman, Software Eng. Group Director at Cadence Design Systems
- Change Team Co-Architect: Adam Matheny, Software Engineer at IBM
- Extensions Steering Group Chair: James Masters, Principal Engineer at Intel
The New Si2 Technical Steering Group Kicks Off
How does Si2 decide on new projects to pursue, leading to new standards and technology? One way is through proposals to the OpenStandards Technology Steering Group (TSG). With technical reps from the Si2 BoD, the TSG is responsible for vetting and engaging leadership and members from Si2 member and non-member companies in new areas for industry alignment and provides technical feedback and recommendations to the Si2 BoD. The TSG provides guidance and structure to existing OWGs and is the gateway for the release of finished work products, including Si2 standards publications and conference presentations. For example, the TSG has reviewed and approved the Si2 Unified Power Model specifications for release to the IEEE 2416 System Power Model standards working group for inclusion in that industry standard. Currently the TSG is working with the AI/ML Schema OWG on milestones and considering a new platform for LLMs. The 2025 TSG members are:
- Kerim Kalafala, IBM, co-chair
- Leigh Anne Clevenger, Si2, co-chair
- Prabhas Kumar, Ansys
- Aparna Dey, Cadence
- Vivek Rajan, Intel
- Narasimhan Narayanan, NXP
- Sorin Soimu, Qualcomm
- Solaiman Rahim, Synopsys
The International Compact Modeling Conference is on June 26, 27 2025
The innovative inaugural International Compact Modeling Conference (ICMC 2025) brings academia and industry partners together to share advances in the development, broad application, and standardization of compact models for semiconductor devices. The conference is co-sponsored by Si2 and the IEEE Electron Devices Society and will be held in San Francisco on June 26-27. The conference recently concluded its call for papers with 60 abstracts being submitted by the deadline. This is an excellent result and will ensure very high-quality papers and presentations at the conference. It will be a great opportunity to share the best practices related to semiconductor device model use and development and increase industry and academic collaboration
Many thanks go to members of the conference committee and TPC members:
- General Chair: Peter Lee , Micron
- Vice Chair: Shahed Reza, Sandia
- TPC Chair: Colin Shaw, Silvaco
- Vice TPC Chair: Gert-Jan Smit, NXP
- Treasurer: Leigh Anne Clevenger, Si2
- Many members of the TPC who will be reviewing the papers.
Si2 CMC Releases Four New Versions of SPICE Models
In February of 2025, Si2’s Compact Model Coalition (CMC) released four new versions of their standardized device models used widely in SPICE (Simulation Program with Integration Circuit Emphasis) circuit simulation tools. The CMC is a coalition of semiconductor companies that standardize these semiconductor device models, and funds leading universities and research institutions to develop, refine, and maintain them for accurate prediction of electrical circuit behavior crucial in chip design. All standard models can be found at CMC Standard Models – Si2. The seven new releases are described below.
High-Voltage MOSFET Models
HiSIM_HV 2.4.4
Developed by Hiroshima University
- Accuracy Improvements
Enhancement of 1/f Noise Calculation: Improved Ey in the 1/f noise calculation under low-field condition by revising default mobility model parameters. - Bug Fixes
QOVJUNC Limitation: Fix to overlap charge modulation to prevent Cgd from occasionally becoming negative.
Bipolar Transistor Models
Mextram 505.5.0
Developed by Auburn University
- Accuracy Improvements
New band-to-band tunneling current (BTBT) and tap-assisted tunneling Current (TAT) models - Bug Fixes
Fixed MINR and MULT handling issue of rbv_t, rbc_t, and re_t
Single and Multi-Gate 3D Transistor Models
BSIM-CMG 112.0.0
Developed by The University of California at Berkeley
- Enhancements and Accuracy Improvements
Enhanced gate to substrate capacitance model for Gate-All-Around (GAA)
Cryogenic temperature model
Trap-assisted tunneling (TAT) GIDL model
Improved IV accuracy both in low and high gate overdrive.
Improved self-heating model for GAAFETs - Bug Fixes
Addressed typos and improved details in the technical manual
Introduced several changes to improve the robustness of the model, preventing divide-by-zero errors and discontinuities.
Address inaccuracies in function evaluations when approaching certain limiting values.
Bulk Planar CMOS Transistor Models
BSIM-BULK 107.2.1
Developed by The University of California at Berkeley
- Bug Fixes
Fixed two bugs which could cause discontinuities in derivates, one in source/drain junction current modeling and one in gmbs modeling
Fixed two bugs in expansion effect modeling
Si2 Joins the Celebration as NSTC Surpasses 100 Members
Si2 today celebrates its membership to the National Semiconductor Technology Center (NSTC) as the public-private consortium established by the CHIPS and Science Act surpasses 100 signed members. Si2 is a core member of the NSTC and supports it’s mission to accelerate U.S.-led semiconductor research and innovation, build a strong domestic semiconductor workforce, and strengthen the United States’ leadership position in the global semiconductor industry.
The NSTC’s mission aligns with Si2’s commitment to provide a unique, collaborative environment and access to shared solutions for users and suppliers from corporations, institutions and academia. In addition to engaging with members across the U.S. semiconductor ecosystem, Si2 members will benefit from the NSTC’s efforts to facilitate access to electronic design automation (EDA) and design resources, tools, and shared datasets.
Operated by Natcast, an independent non-profit entity, the mission of the NSTC is to convene members from across the U.S. semiconductor value chain, academia, and government to advance three shared and strategic goals: strengthen U.S. semiconductor leadership; reduce time from lab-to-fab; and expand the U.S. semiconductor workforce. NSTC Members benefit from access to leading-edge research, state-of-the-art facilities, shared physical and digital assets, dedicated events and collaboration opportunities, and employer-driven workforce development programming.
To view a comprehensive list of NSTC Members and learn how to join, visit natcast.org. For more information on opportunities to engage with Si2 on NSTC-related efforts, please visit our website at si2.org.
Leigh Anne Clevenger (Si2 VP) elected to Chair of CAEML Industry Advisory Board
Si2 is a member of the Center for Advanced Electronics through Machine Learning (CAEML), an NSF Industry/University Cooperative Research Center. CAEML’s research mission is to apply machine learning to the design of optimized microelectronic circuits and systems, thereby increasing the efficiency of electronic design automation (EDA), resulting in reduced design cycle time and radically improved reliability.
For the past two years as vice-chair of the CAEML IAB, Leigh Anne worked closely with the chair on guiding development of Request for Proposals, proposal reviews, and final voting decisions on university project funding. She actively participates in the planning and leadership of the bi-annual meetings, and is a project mentor on 3D-IC, optical/electrical design using AI, and EDA data security. Leigh Anne brings insight into publicly available results from CAEML back to Si2 member companies. With her experience in the semiconductor industry, attention to detail, and ability to drive consensus decisions, she was elected CAEML IAB chair for 2025.
For more information on CAEML member companies and current research see https://caeml.illinois.edu/research/current-projects
OpenAccess Coalition Coloring Group Makes 1.1 Release of oaxColor
In January, the OpenAccess Coalition Coloring Work Group made a new release of oaxColor that supports new multi-pattern technologies. In 2012, Cadence Design Systems contributed a specification describing the extension of OpenAccess to represent multi-pattern technology, aka coloring. That specification has been a guide for developing the newest version of oaxColor extension, Release 1.1. This release extends the OpenAccess API, allowing users to implement their own (usually proprietary) process for multi-pattern technology. The work group has implemented everything described in the initial document, so the extension is effectively completed in this latest release. The work group is alert for possible bugs and enhancements, but the path to implementation should be uninterrupted by changes to the extension moving forward. In addition to C++ for use with the OpenAccess Reference Implementation, Python and Ruby are supported companions to the oaScript API. Congratulations to the Coloring Work Group, led by Ben Hoefer and Rajiv Subramanian of Intel, for their contributions to the OpenAccess Coalition.