” Standard model development is a continuous process of Si development and gradual inclusion of newer physical effects working closely with model developers. WG meetings in the CMC are the best place for that. While all aspects of modeling updates are important, prioritization is possible looking at time sensitive customer needs and new features in standard models can be propagated consistently in available standard tools through the CMC. This is the quickest and most complete path to deliver working solutions to customers in need. ” – Tanvir Morshed, GlobalFoundries
Dr. Chenming Hu
Chenming Hu received the US Medal of Technology and Innovation from President Obama in the White House in 2016 “for pioneering innovations in microelectronics including reliability technologies, the first industry-standard model for circuit design, and the first 3-dimensional transistors, which radically advanced semiconductor technology.” From 2001-2004, he was the Chief Technology Officer of TSMC, world’s largest IC foundry. In 2021, IEEE, the world’s largest technical association, presented him its highest award – IEEE Medal of Honor. He is TSMC Distinguished Professor Emeritus at University of California, Berkeley.
Dr. Mitiko Miura-Mattausch
Since 1996, Mitiko Miura-Mattausch has been a Professor at the Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima University, where she leads the Ultra Scaled Devices Laboratory. From 1981 to 1984, she was a Researcher at the Max-Planck Institute for Solid-State Physics, Stuttgart, Germany. From 1984 to 1996, she was with the Corporate Research and Development, Siemens AG, Munich, Germany, working on hot electron problems in MOSFETs, the development of bipolar transistors, and analytical modeling of deep sub-micrometer MOSFETs for circuit simulation. She has more than 300 publications and three books, is an IEEE fellow since 2001, and was honored by several awards.
Dr. Michael Schröter
Michael Schröter has been a Full Professor at the University of Technology at Dresden, Germany, since 1999, and a Research Scientist at UC San Diego, USA, from 2003 to 2018. Before, he held engineering and management positions at Nortel/BNR, Rockwell/Conexant, and RFNano. He has been the author of the bipolar transistor compact model HICUM, a worldwide standard since 2003, has co-authored two textbooks and over 300 peer reviewed publications and has contributed several invited book chapters.
Dr. Schröter was an initiator and the Technical Project Manager for the EU projects DOTFIVE (2008-2011) and DOTSEVEN (2012-2016) that led to SiGe HBT technologies with world-record performance. He co-founded XMOD Technologies in Bordeaux, France, and, more recently, SemiMod GmbH in Dresden, Germany.
Dr. Guofu Niu
Dr. Niu has been a Full Professor at Auburn University in the department of electrical and computer engineering since 2004. His research and teaching activities include SiGe devices, RF CMOS, high-frequency on-chip characterization, noise, radiation effects, low temperature electronics, compact modeling and TCAD. He has published over 100 journal papers and over 100 conference papers, and is the co-author of the book Silicon-Germanium Heterojunction Bipolar Transistors, Artech House, 2003 (with John Cressler), and many book chapters. Dr. Niu served as an Editor of IEEE Transactions on Electron Devices from 2012 to 2021.
Dr. Thierry Poiroux, Dr. Olivier Rozeau
Dr. Poiroux is the Head of the Simulation and Compact Model Laboratory at CEA-Leti. In this role, he leads a team devoted to the modeling and simulation for microelectronics processes and devices. The Lab’s activities cover atomistic simulation, TCAD, multiphysics simulation and SPICE modeling. Personal background: advanced CMOS device development, compact model of transistors.
Dr. Rozeau is a researcher at CEA-Leti in the Simulation and Compact Model Laboratory. He received the Ph.D. degree from Grenoble INP France in 2000. He has more than 20 years of experience in device compact modeling and characterization. He is developer of industry standard PSP model for bulk MOSFETs and Leti-UTSOI for FDSOI MOSFETs. His other research interests in modeling are advanced multigate MOSFET and photonic devices.
Dr. Sourabh Khandelwal
Dr. Sourabh Khandelwal is a faculty member in the School of Engineering at the Macquarie University, Sydney, Australia. He is the lead developer of the ASM-HEMT compact model, which is a new industry standard for GaN RF and power devices. He has been a research faculty at the University of South Florida. Prior to that, he was Manager of the Berkeley Device Modeling Center and a Postdoctoral Researcher at the BSIM group at the University of California Berkeley. He has published three books, and over 100 research articles in the area of semiconductor device modeling and circuit simulations.
Dr. Lan Wei
Prof. Lan Wei received her B. S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M. S. and Ph. D. in Electrical Engineering from Stanford University, Stanford, USA in 2007 and 2010, respectively. She is currently an Assistant Professor at the University of Waterloo, Waterloo, Canada. Before her current position, she worked as a Member of Technical Staff at Altera Corporation (now part of Intel Corporation) in California, and as a Post-doctoral Associate at Microsystems Technology Laboratories in Massachusetts Institute of Technology. She has intensive experience in device physics-based compact modeling, including developing compact models for carbon-nanotube transistors and the MIT virtual-source transistor compact model for silicon MOSFET and GaN HEMT. Her other research interests include device-circuit interactive design and optimization, integrated nanoelectronic systems with low-dimensional materials, cryogenic CMOS device modeling and circuit design for quantum computing.
CMC annual membership funds from all members combine to fund research and collaborative group support to make semiconductor device standardization a reality. Proven standards have been evolving for decades and new standards continue to be added, providing tremendous savings to industry by the CMC taking responsibility for supervision of the model standardization, maintenance, and validation.
Participating in international quarterly gatherings give your company members real-time deep dives on the foundations of major technologies with profound implications on the next generation of semiconductor designs. Consensus by member companies, along with expert opinions from the world’s top device physics researchers, determines these semiconductor industry standards.
For EDA simulation tool suppliers, your CMC funding will give your circuit simulation development team early access to research source code under discussion by the model work group for the standard device models most critical to your customers to accelerate time to implementation and release.
CMC-developed resources have 18-month exclusive production use for CMC member companies before public release, including the Open Model Interface (OMI) which supports the heterogeneously integrated technologies on the horizon of semiconductor design.
Publicly available standard device models from the CMC enable all semiconductor research institutions and academia to do wide-ranging theoretical research which can be transferred to the industry. This ensures that the next generation of design engineers have experience with standard models for the latest technologies.
The CMC is a community of experts in the application of device modeling to semiconductor design and manufacture who apply their professional expertise to defining, testing, and validating new requirements and enhancements for device model standardization through providing a single voice to university and research institution device model developers.
The majority of your CMC funding goes directly to model development by research institutions and universities. Through funding selected models, your company has the opportunity to influence new development by having a voice on features and improvements to implement. You obtain early access to development code to test and validate models before they are publicly released, allowing you to quickly adopt the new models in your designs and PDKs.
Through a four-step model standardization process, the resulting CMC standard models are trusted by industry, and incorporated into all major EDA circuit simulation tools.
The CMC members include all major EDA Simulation Tool suppliers who see the value in influencing and gaining early access to standard device models. Integrating these standard device models is fundamental to all detailed circuit simulation tools. As an EDA simulation tool product owner, your CMC membership will give your development team early access to pre-production source code under discussion by the model work group for the standard device models.
Focus on the models most critical to your customers to accelerate time to implementation and release. As a member of a model work group you talk directly with your customers in that group and with the device model developers to add the most impactful model features. The released models have been validated by the researchers and a QA validation tool suite is available to simulation developers for greater confidence prior to integration into your simulation tools.
The CMC is the only organization where all major semiconductor foundries can collaborate to influence fundamental device model research. As a foundry device engineer, the CMC model standardization process guarantees a consistent set of model parameters across EDA simulator implementations. Parameters that you need for production manufacturing are provided to all EDA simulation suppliers. These consistent parameters sets are then available to all industry and research design teams.
As technology develops into the most advanced nodes, you can influence the research to support advanced semiconductor technologies. As a member of a CMC work group, you have early access to the model parameters and algorithms, enabling efficient and consistent Process Design Kit development.
The majority of all digital and analog circuits designed in industry and academia rely on the CMC standard models. You will find the CMC models as the foundation of every major foundry PDK. As a designer of today’s advanced semiconductor circuits, you require physics-based device models developed through fundamental research. Learn how to use these models more effectively through work with CMC developers and other members. CMC standards include CMOS, Multi-Gate, Silicon-on-Insulator, Bi-Polar, and Gallium-Nitride, and more are added as requested by the member companies.
Standard models are integrated into all detailed circuit simulators, whether from EDA suppliers, in-house, or open source. You’ll be connected to the device model advocates from EDA supplier companies as a CMC member. The CMC QA process validates the device models in a wide range of operating conditions from both the model developers and the EDA circuit simulation tool providers.
As you design for reliability, you can build on the Open Model Interface (OMI) which supports the heterogeneously integrated technologies on the horizon of semiconductor design. Latest releases are available exclusively for CMC member companies for 18-months before public release. OMI has expanded functionality beyond the simple aging sweep to allow greater flexibility in mixing stresses with evaluation after a number of stress levels to explore reliability. This makes OMI universally applicable to all models and reveals the possibilities this brings to device evaluation.
The CMC is a member-led organization with established governance policies and oversight in keeping with the industry trust in their device model standards. The CMC governance by the officers, work group collaboration, QA testing and formal standardization process all combine to enable semiconductor industry success with these robust and trusted foundational device models.
The CMC officers oversee the operation of the CMC, including quarterly meetings and policy updates. The Chair is also the liaison to organizations outside of the CMC. They are elected to 2-year terms.
There are CMC Work Groups for each standard model as well as for models being evaluated for standardization, APIs and utilities. A Work Group can be established with a chair and 3-4 additional member companies. The WG Chair coordinates regular meetings and on-line communication with the model developer and the WG. This includes vetting candidate models, discussion of beta and production releases, and model testing.
An extensive model Quality Assurance (QA) checklist and associated test suite is developed and maintained by the CMC exclusively for members and model developers. These tests provide common criteria to judge coverage for model operation and for backward compatibility during circuit simulation.
The four-phase standardization process is the expected discovery path for new proposed model standards.
