Ramesh Narayanaswamy is an R&D Scientist at Synopsys. Ramesh works on Synopsys’ Verification and Design Products, specializing in Simulation Performance/Acceleration, and ML/AI/GenAI Applications in EDA. Ramesh leads the development of GenAI RTL Design and Verification Agents. Ramesh has built Domain Specific Accelerators targeting Many Core, GPU, ASIC, and FPGA Platforms. Over a 30+ year career Ramesh has architected and led development of Simulation Software, Simulation Acceleration ASICs & Compilers, and FPGA-based Emulators. Tools Ramesh built have been used to verify Processor and Peripheral Chips in many generations of GPUs, Mobile devices, and Compute Servers. He has 12 granted patents.