Si2 Compact Model Coalition to Support CEA-Leti SPICE Simulation Model
The Si2 Compact Model Coalition has announced the approval and financial support of L-UTSOI, a new ultra-thin, silicon-on-insulator transistor simulation model developed by CEA-Leti, a France-based research institute for electronics and information technologies.
L-UTSOI was selected for support by CMC, a coalition of 30 semiconductor companies that standardizes semiconductor models used in a class of circuit simulation tools called SPICE, or Simulation Program with Integration Circuit Emphasis. Manufacturers save time and money by simulating the performance of new or enhanced integrated circuit designs before the ICs are manufactured. The CMC funds leading universities and research institutions to develop, refine and maintain SPICE models, which are incorporated into widely used semiconductor design tools.
Silicon-on-insulator uses a thin layer of insulating oxide that semiconductor manufacturers insert between a silicon substrate and the top silicon layer. That insulating layer improves power efficiency and reliability. When compared with conventional bulk-silicon CMOS devices, SOI designs are well-suited for low-cost, low-power applications, such as automotive and the Internet of Things.
“CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.”
André Juge, working group co-chair and fellow member of technical staff at STMicroelectronics, stated, “L-UTSOI features accurate modeling of ultra-thin body and box fully-depleted SOI devices, combined with high predictiveness and numerical performance for simulation of circuits operating in a wide range of applications. For several years, starting at the 28-nanometer technology node and below, L-UTSOI has been a key enabler for design technology co-optimization.”
“CMC provides a rare opportunity to work in tandem with the simulator suppliers that are implementing our code, and the end-users which create the designs,” said Thierry Poiroux, head of the Simulation and Compact Modeling Laboratory at CEA-Leti. “Regular CMC meetings ensure a quick response to feature and bug-fix requests. We look forward to this same support from the CMC stakeholders implementing and using the L-UTSOI model.”
“As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer request for model support, as we continue to add value to their membership. ”