Si2 provides a unique collaborative environment and access to shared solutions for users and suppliers from corporations, institutions and academia. Si2 solutions are co-developed to permit innovation while guaranteeing compatibility with trusted standards. Some members have leadership roles and participate broadly across Si2. Some members focus on specific areas of interest. Others join to primarily gain access to Si2 solutions. All are welcome. As we approach our annual renewal cycle it is good to reflect on some accomplishments over the past twelve months. Below is a summary of some highlights.
The OpenAccess Coalition – OAC: OpenAccess is an extensible API on top of a managed multi-user design database that enables the interoperability required by hybrid design flows. The OpenAccess Coalition constantly synchronizes this API and database with other EDA tools through constant collaboration between the top EDA suppliers, IP providers, design companies, and the integrator company. Highlights:
- Si2 migrated the OAC Member Portal to the Causeway Tool. Causeway’s business model better fits Si2 and will enable the OAC to grow the ecosystem through our new user capacity.
- The Change Team pressed forward on the base Platform Matrix. The release of data model six-two will take the reference implementation to Red Hat Linux level 8.4 and gcc 9.3, enabling the use of C++20. The extensions will closely follow the reference implementation.
- Carlo Barrientos and Christy Pack were added to the OAC Support team. Carlo, who has design experience, will support OpenAccess extensions. Christy will focus on productizing the oaScript API in Python, Ruby, and TCL.
- Chris Falkowski continued to make OpenAccess easier to use. We are in the Beta Test with the configuration/builder tool set. These tools help users prepare the environment for building OpenAccess and the Extensions, avoiding the frustrating try-fail-fix cycle. Once the builder tool shows that the environment is ready, the user can launch the long compile, confident that it will be completed successfully.
The Compact Model Coalition – CMC: “Standard model development is a continuous process of Si development and gradual inclusion of newer physical effects working closely with model developers. WG meetings in the CMC are the best place for that. While all aspects of modeling updates are important, prioritization is possible looking at time sensitive customer needs and new features in standard models can be propagated consistently in available standard tools through the CMC. This is the quickest and most complete path to deliver working solutions to customers in need.” -CMC Member. Highlights:
- Planning is in full swing for the inaugural ICMC conference, June 26-27, 2025, at the Clift Royal Sonesta at Union Square, San Francisco. Scheduled so DAC 2025 attendees can easily participate, this is “Not just another modeling conference,” and uniquely focuses on compact semiconductor device model applications, model Q&A, parameter extraction methodologies, model development methods, and model standardization, as well as model development itself. Task force leadership includes Peter Lee, Micron, Shahed Reza, Sandia Labs, Colin Shaw, Silvaco, and Gert-Jan Smit, NXP. Be looking for the Call for Papers!
- Strong innovation continues from the CMC model developers, guided by industry working groups. These standard models are the foundation for our semiconductor industry. Since September 2023 there have been production model releases for Bulk MOSFET, SOI MOSFET, Bipolar, GaN HEMT, and Open Model Interface models. The EDA circuit simulation vendor members of the CMC have early access to add these production models to their commercial offerings. A complete listing of the production releases is below:
| Model Name | Version Number | Release Date |
| PSP | 104.0.0 | 9/11/23 |
| BSIM-SOI | 100.1.0 | 10/17/23 |
| OMI | 2.0.0 | 2/5/24 |
| MVSG | 4.0.0 | 4/16/24 |
| L_UTSOI | 102.8.0 | 5/31/24 |
| HICUM_L2 | 3.1.0 | 6/20/24 |
| ASM-HEMT | 101.5.0 | 8/19/24 |
| BSIM-BULK | 107.2.0 | 8/26/24 |
The Unified Power and Thermal Coalition – UPTC: UPTC members participate in and benefit from the co-development of system level power models, utilities, and methodologies in support of the IEEE 2416 UPM standard. Coalition members also consider cross-domain power impacts, such as thermal, and drive the development of these aspects in the standard, thereby supporting integrated power-thermal workflows. Highlights:
- The work of Si2 UPTC and the IEEE 2416 are highlighted in the August 14, 2024 Semiconductor Engineering article by Brian Bailey, “Reusable Power Models,” based on an in-person roundtable which included Nagu Dhanwada, IBM, Sri Chilukuri, Qualcomm, and Daniel Cross, Cadence. This in-depth discussion covers aspects of power modeling ranging from system architecture requirements to reuse of existing models to leveraging multiple levels of abstractions.
- Proof-of-Concept demonstrations with SoC and Foundry members of the UPTC are building on early successes with publicly available designs and standard cells, such as the AES 128 and Nangate 15nm. The scope of PoCs with Qualcomm and Samsung have expanded to production implementations of UPM/IEEE 2416 models. UPTC recently welcomed NXP, and we look forward to working with them on their UPM/IEEE 2416 methodology.
- Collaboration between Daniel Cross, Cadence, Rhett Davis, NC State, and the UPM Working Group produced the successful DAC ’24 Poster presented by UPM Working Group members, “Advancing Low Power Design in the Era of Rising Energy Footprints: Insights from IEEE 2416 Standard and Future Extensions.” This showed for the first time the results that will be possible using method for Analog/Mixed Signal representation enabled by elements in the new IEEE 2416-2025 standard release. The UPM WG and Si2 engineering staff are actively building on this work for an interactive tutorial planned for DAC ’25.
- With encouragement from the Si2 BoD and the UPTC PoC with Qualcomm, Si2 engineering staff has implemented more robust system-level power analysis support to represent models of system states and parameters using complex expressions and tables. Schema elements for these innovations are planned to be made available to industry through the upcoming IEEE 2416-2025 standard release.
The Si2 Base membership allows members to participate in any Special Interest Group (SIG). They are collaborative groups that address the issues of the SIG’s members consistent with the purpose of the Initiative. SIGs generally explore emerging areas of interest with the goal of narrowing the focus and proposing specific actions.
The AI/ML In EDA SIG: Successful application of AI/ML is critical for continued progress in chip and system design. The AI/ML SIG includes industry experts on machine learning, chip design, and EDA. SIG members work with these experts to explore how best to apply AI for chip design. Highlights
- Si2 sponsored an insightful panel discussion at The First IEEE International Workshop on LLM-Aided Design (LAD’24) on June 28, 2024, held at the IBM Almaden Research Center with over 200 attendees. The conference organizers praised the panel for giving the mostly academic audience a reality check on scaling and testing needed to move Generative AI from theory to production for the semiconductor industry.
- The industry and University Panelists were: Akhilesh Kumar, Ansys, Ioannis Savidis, Drexel University, Mike Kazda, IBM, Srinivas Bodapati, Intel, Sid Dhodhi, Nvidia, Ivan Kissiov, Siemens EDA, Ilhami Torunoglu, Siemens EDA. The panel discussed their positions on:
- Generative AI for semiconductor from architecture to fab: A pipedream? Or ready for prime time?
- How is Gen AI useful to us in semiconductor design?
- What is a successful AI-centric mindset to approach Design Automation?
- What are the challenges of using this technology in production, not just in a PoC?
- What are the implications of using LLM from a security perspective?
- What is the direction of large models vs limited, tuned models – how does this effect the methodology flow?
- SIG members decided to continue the LLM discussion for on-going knowledge sharing on LLMs related to EDA and semiconductors, with a goal of deciding where Si2 can add value for the industry and academia. Upcoming topics to be presented by industry and academic members include Framework/infrastructure for LLM, EDA-Corpus and OpenRoad-Assistant, Fine-tuning LLMs, knowledge transfer, and small language models, and LLM in context of global optimization, breaking down the traditional EDA silos. All Si2Base members are welcome!
The 3D IC SIG: 3D-IC brings together previously separate domains of chip and system design with package design. Also, this technology brings additional challenges in power and thermal design and in testability. Advanced 3D-IC packaging has been called a “wild west,” where a lack of standards means that each company that wants to participate has to figure out a lot on its own. Members of the 3D-IC SIG work together with experts from EDA companies, design companies, foundries, and OSATs to find opportunities for standards and beneficial shared utilities. Highlights
- Presentation on Open Compute Project at December ‘23 Si2 Strategic Workshop
- Documenting the 3D-IC landscape through attending conferences and industry work groups
- Marc Rose, Si2, presented to the 2024 JEDEC and OCP Standards for Chiplet Design with 3DIC Packaging Workshop, “Si2 3D-IC ADR Proposal”
The Si2 Base membership also allows members to participate in any OpenStandards Working Group (OWG). Open Standards Working Groups (OWGs) are chartered by the Si2 Board of Directors to produce Si2 standards and other intellectual property (“IP”) to support design flows. The OWG members develop requirements, review candidate technologies or services, propose resolution of issues and develop proposals for proof-of-concepts, prototypes, reference materials, compliance suites, standards, specifications and guidelines.
A Common AI/ML Schema for Academia and Industry Collaboration: The focus of this OWG is on a standardized schema specification which provides good support for AI/ML algorithms and for data analytics. The OWG will specify requirements, priorities and use cases and feed those into two existing schema projects in academia. Highlights
- The newly proposed AI/ML Schema work group will be focused on developing use cases and requirements for standard schema to represent processed data for analytics and machine learning, facilitating academic/industry collaboration. This is based on requirements first developed by the 2022-2023 SPEED API Working Group, and the candidate schemas were identified through the AI/ML in EDA SIG. Initial participants are companies from our current AI/ML SIG, and additional Si2 Base member companies are welcome to join.
- The prospective members voted to fund universities to enhance their schemas with our work group requirements. Si2 is going to fund Prof. Ioannis Savidis at Drexel University and Prof. Vidya Chhabria at Arizona State University for the 2024-2025 school year to support one graduate student each. This is an example of how Si2 members combine resources to achieve a common goal.
Si2 2024 Award Honorees
Power of Partnership Award
The Si2 Power of Partnerships Awards recognize the Si2 collaborative teams that have made significant contributions to the advancement of electronic design automation. The two winners of the 2024 POP award are shown below. Congratulations and thank you to all of the recipients!
The Si2 Compact Model Coalition Open Model Interface Working Group
Notable Accomplsihments:
- Released a groundbreaking new version to support non-MOSFET devices.
- Paves the way for heterogeneously integrated technologies on the cutting edge of semiconductor design.
- Transcended its initial limitations to encompass a more diverse set of devices, including bipolar models.
- Holds universal applicability across all models, unlocking numerous possibilities for device evaluation and reliability.
Team Members:
- Colin Shaw, Chair, Silvaco
- Ahmed Abo-Elhadid, Siemens
- Geoffrey Coram, Analog Devices
- Volker Kubrak, Infineon
- Jushan Xie, Cadence Design Systems
- Jooyoung Song, Samsung Electronics
- Che-An “Andy” Lee, Synopsys
- Rhett Davis, NCSU
The Cadence Design Systems OpenAccess Implementation Team
Notable Accomplishments:
- First-time Power of Partnership Corporate Member Award winner.
- Dynamic development arm of Cadence Design Systems’ OpenAccess integration effort.
- Collaborates closely with the Si2 OpenAccess Change Team and other corporate members of the Si2 OpenAccess Coalition.
- Responsible for the enhancements and new capabilities that ensure the OpenAccess API remains at the cutting edge of the EDA industry’s changes.
Team Members:
- Shawn McEvoy, Team Leader
- Alex Wong
- Shelly Evans
- Vincent Desbieys
- Radu Ursu
- Mike Prikhodko
- Christophe Vial
- Olivier Touzet
- Johannes Grad
Si2 Quarterly Pinnacle Award Honorees for 2024
The quarterly Si2 Pinnacle Awards recognize the exceptional efforts of individuals who volunteer their time and made exceptional efforts in support of Si2 in the past year.
Q1 2024: Awarded to Shahriar Moinan (Broadcom) for his exceptional efforts as chair of the Si2 Compact Model Coalition Model Quality Assurance and Release Work Group.
Q2 2024: Awarded to Larg Weiland (PDF Solutions) for his exceptional contributions to SI2 via his involvement in the OpenAccess Coalition.
Q3 2024: Daniel Cross (Cadence Design Systems) for his exceptional efforts with the Si2 Unified Power Model Working Group, the Si2 Unified Power and Thermal Coalition, and the IEEE 2416 and 1801 Working Groups.
