DAC 2020 Video Tutorial: System-Level Power Analysis with Unified Power Models
Learn how to develop UPM/2416 power data models, configure them to interoperate with UPF/1801 power state models, and use them with emerging system-level power analysis tools.
- Nagu Dhanwada, IBM
Introduction, Mission and Motivation
- Rhett Davis, NC State University
UPM for the IP Provider (25:24)
UPM for the EDA Developer (40:30)
- Jerry Frenkil, Silicon Integration Initiative
UPM for the System Architect (49:09)
- David Ratchkoff, Thrace Systems
UPM for the System Designer (1:08:4)
The demand for increased power efficiency in both wired and wireless applications continues to grow unabated. This demand has generated considerable interest in low power design methods that have become well established at the RTL, gate, and physical, levels. While it’s accepted that opportunities for reducing power at the system level are high, low power design automation at the system level has lagged. One primary reason for that lag has been a lack of system-level IP block power models, particularly of standardized, inter-operable, models. This has in turn motivated the development of Unified Power Models (UPM), recently standardized as IEEE 2416-2019.
This is the first tutorial since the standard’s release in summer 2019. It addresses how this new modeling technology is used and the novel, related tools and methodology it enables. This new standard was developed to meet the power modeling needs of three distinct groups of users: IP providers and model producers, system architects and SoC designers, and EDA developers. UPM/2416’s rich semantics facilitate easy and interoperable model exchange by providing four different data representations – scalars, tables, expressions, and contributors (process, voltage, and temperature-independent proxies for energy and power)– and three different modeling levels – bit, system, and multi-level. UPM/2416 models also facilitate efficient electro-thermal analysis by providing voltage and temperature independent modeling enabling the late-binding of voltage and temperature values at analysis run time. The tutorial will begin with an overview of the standard.
This overview is followed by detailed descriptions of the various data representations and modeling levels, elaborating on the applicability of each to different modeling situations. The novel UPM/2416 system-level semantics is illustrated using specific examples of power models for common IP blocks, such as a memory and a RISC-V processor. Bottom-up models, based on design data and power contributors, and top-down models, based on measured or simulated data, are described in detail. The examples will include details of how UPM/2416 power data models inter-operate with UPF/1801 power state models.
Finally, use of these models is demonstrated by running live power analyses using emerging UPM/2416 compatible power analysis tools. These demonstrations will focus on new capabilities, such as the late-binding of PVT conditions to the models at analysis run time, mitigating the need for multiple libraries at different PVT combinations. This tutorial is for designers of power and temperature constrained devices and related design automation. It will provide detailed insights into advanced power modeling and analysis techniques using UPM/2416.
Attendees will learn how to develop UPM/2416 power data models, configure them to interoperate with UPF/1801 power state models, and use them with emerging system-level power analysis tools.